面向 Zynq-7000 XC7Z045 SoC 的 ZC706 评估板
用户指南
UG954 （v1.8） 2019 年 8 月 6 日
ZC706 评估板用户指南 www.xilinx.com
2
UG954 （v1.8） 2019 年 8 月 6 日
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修订历史记录
下表显示了此文档的修订历史记录。
日期
版本
校订
10/08/2012
1.0
初始 Xilinx 版本。
11/21/2012
1.1
在 ZC706 评估板功能部分、表 1-1、用户 I/O 部分、图 1-26 和表 1-28 中添加了额外的用户 LED。在表 1-1 中，添加了 10/100/1000 以太网 PHY、用户按钮、用户 DIP 开关和 FPGA PROG 按钮的风扇接收器信息和更新的注释。添加了 Encryption Key Backup Circuit 部分。更新了 DDR3 SODIMM 内存 （PL） 部分的第二段。
更新了 SD 卡接口部分的第二段。更新了表 1-11。在 HDMI 视频输出部分的第一段中添加了 U53 信息。在 Real Time Clock （RTC） 部分添加了第四个项目符号。更新图 1-24。在表 1-28 中新增引脚 A17。更新图 1-33。替换了附录 C 中的 UCF。添加了对其他资源的附加引用。
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04/24/2013
1.2
第 1 章，ZC706 评估板功能：表 1-1 功能说明现在链接到本书中的相应部分。替换了图 1-3、图 1-34 和图 1-35。表 1-2 已删除，因为它与表 1-11 重复。表 1-2：添加了交换机 SW11 配置选项设置。FMC 连接器 JTAG 旁路，第 35 页已更新。图 1-18 下面的默认车道大小信息已更改。图 1-19 添加了 PCI Express Lane Size Select Jumper J19。引脚 18 和 19 的名称在表 1-17 中发生了变化。表 1-25 中 I C 总线 PMBUS_DATA/CLOCK 的地址发生了变化。参考标号 DS35 已添加到表 1-27 中。用户 I/O 第 59 页部分中的标注编号现在链接到表 1-1。SW13 信息被添加到用户按钮部分，第 61 页。在表 1-33 中，J5 引脚 H22 改为 XC7Z045（U1）引脚 AH26，H23 改为 AH27。添加了 ZC706 Board Power System（第 74 页）部分。VADJ Voltage Control，第 81 页中更改了电压电平。修改表 1-37，增加表 1-38。
附录 A，默认开关和跳线设置：表 A-1 中的 SW11 选择已更改。附录 F，监管和合规性信息：添加了指向主答复记录的链接。
07/31/2013
1.3
更新了表 1-22。将附录 C，Xilinx 约束文件中的主用户约束文件 （UCF） 列表替换为主 Xilinx 设计约束 （XDC） 列表。更新了整个文档中的引用。
04/28/2015
1.4
将“LMZ22000 系列稳压器描述”更新为 LMZ31500 和 LMZ31700 系列稳压器描述。更新了表 1-4、表 1-7、表 1-13、表 1-23、表 1-28 至表 1-30、表 1-32 至表 1-34、表 1-36 和表 A-2。添加了图 A-1。更新了附录 C，Xilinx 约束文件。
09/10/2015
1.5
更新了 J48 标头跳线设置（表 1-7 中的第三行）。
03/29/2016
1.6
将图 1-33 中 C6 的值从 270 pF 更新为 5600 pF。
07/01/2018
1.7
仅限编辑更新。没有技术内容更新。
08/06/2019
1.8
将图 1-27 从 VADJ 更新为 VCC1V5_PL。附录 F，法规和合规性信息：添加了指向主应答记录的更新链接。
日期
版本
校订
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UG954 （v1.8） 2019 年 8 月 6 日
目录
修订历史 2
第 1 章：ZC706 评估板特性
概述
7
ZC706 评估板特性 7
框图10
电路板布局10
放电注意事项
11
功能描述
15
Zynq-7000 XC7Z045 SoC 15 设备配置 16
加密密钥备份电路 17
I/O 电压轨 18
DDR3 SODIMM 内存 （PL） 19
DDR3 组件内存 （PS23
四通道 SPI 闪存26
USB 2.0 ULPI 收发器29
SD 卡接口31
可编程逻辑 JTAG 编程选项33
可编程逻辑 JTAG Select 开关 33
FMC 连接器 JTAG 旁路 35
时钟生成 35系统时钟 36
可编程用户时钟 37
用户 SMA 时钟源 38
处理系统 Clock Source 39
GTX SMA 时钟 （SMA_MGT_REFCLK_P 和 SMA_MGT_REFCLK_N 39
抖动衰减时钟 40
GTX 收发器 41
PCI Express 端点连接46
SFP/SFP+ 模块连接器48
10/100/1000 Mb/s 三速以太网 PHY （PS49）
以太网 PHY 时钟源 50 USB 转 UART 桥接器 51
HDMI 视频输出52
I2C 总线55
实时时钟 （RTC57
状态和用户 LED58
以太网 PHY 用户 LED59
用户 I/O59
用户 LED 60
用户按钮 61
GPIO 拨码开关 62
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用户 PMOD GPIO 接头 62 开关 64 电源开/关滑动开关 64
Program_B 按钮 65
PS 开机和系统重置按钮 66
FPGA 夹层 （FMC） 卡接口 67 HPC 连接器 J37 67
LPC 连接器 J5 71
ZC706 板电源系统 74 UCD90120A 描述 74
LMZ31500 和 LMZ31700 系列稳压器描述 74
XADC 电源系统测量 77
电源管理 79
VADJ 电压控制器 81
SoC 可编程逻辑 （PL） 电压控制 82
监控电压和电流 82
网赌最正规的平台 84
XADC 模数转换器 85
附录 A：默认开关和跳线设置
开关
88
运动员
89
附录 B：VITA 57.1 FMC 连接器引脚布局
附录 C：Xilinx 约束文件
附录 D：板设置
在 PC 机箱中安装 ZC706 板
95
附录 E：主板规格
尺寸
97
环境的
97
温度 97
湿度 97
工作电压 97
附录 F：监管和合规信息
概述
98
符合性声明
98
CE 指令
98
CE 标准
98
电磁兼容性 99
安全 99
标记
99
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UG954 （v1.8） 2019 年 8 月 6 日
附录 G：其他资源
Xilinx 资源
101
解决方案中心
101
引用
101
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UG954 （v1.8） 2019 年 8 月 6 日
第一章
ZC706 评估板特性
概述
面向 XC7Z045 SoC 的 ZC706 评估板为开发和评估针对 Zynq-7000® XC7Z045-2FFG900C SoC 的设计提供了硬件环境。ZC706 评估板提供许多嵌入式处理系统通用的功能，包括 DDR3 SODIMM 和组件存储器、四通道 PCI Express® 接口、以太网 PHY、通用 I/O 和两个 UART 接口。其他功能可以是
支持使用连接到低引脚数 （LPC） FMC 和高引脚数 （HPC） FMC 连接器的 VITA-57 FPGA 夹层卡 （FMC）。
ZC706 评估板特性
此处列出了 ZC706 评估板的功能。从第 15 页开始的功能描述中提供了每个功能的详细信息。
•
Zynq-7000 XC7Z045-2FFG900C SoC
•
可编程逻辑 （PL） 侧的 1 GB DDR3 内存 SODIMM
•
处理系统 （PS） 侧的 1 GB DDR3 组件内存（四个 [256 Mb x 8] 个器件）
•
两个 128 Mb Quad-SPI （QSPI） 闪存（Dual Quad-SPI）
•
USB 2.0 ULPI（UTMI+ 低引脚接口）收发器，带 micro-B USB 连接器
•
安全数字 （SD） 连接器
•
USB JTAG 接口，通过带有 micro-B USB 连接器的 Digilent 模块
•
时钟源：
°
固定 200 MHz LVDS 振荡器（差分）
°
我 C
可编程 LVDS 振荡器 （差分）
°
固定 33.33 MHz LVCMOS 振荡器（单端）
°
超小型型 A （SMA） 连接器（差分）
°
用于 GTX 收发器时钟（差分）的 SMA 连接器
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UG954 （v1.8） 2019 年 8 月 6 日
概述
•
GTX 收发器
°
FMC HPC 连接器（8 个 GTX 收发器）
°
FMC LPC 连接器（一个 GTX 收发器）
°
SMA 连接器（TX、RX 和 REFCLK 各一对）
°
PCI Express（四通道）
°
小型可插拔增强型 （SFP+） 连接器
°
以太网 PHY RGMII 接口
•
PCI Express 端点连接
°
Gen1 4 通道 （x4）
°
Gen2 4 通道 （x4）
•
SFP+ 连接器
•
以太网 PHY RGMII 接口，带 RJ-45 连接器
•
带 mini-B USB 连接器的 USB 转 UART 桥接器
•
带 HDMI 连接器的 HDMI 编解码器
•
I C 总线
•
I C 总线多路复用至：
°
Si570 用户时钟
°
ADV7511 HDMI 编解码器
°
M24C08 EEPROM （1 kB）
°
1 对 16 TCA6416APWR 端口扩展器
°
DDR3 SODIMM
°
RTC-8564JE 实时时钟
°
FMC HPC 连接器
°
FMC LPC 连接器
°
PMBUS 数据/时钟
•
状态 LED：
°
以太网状态
°
TI 电源正常
°
线性电源良好
°
PS DDR3 组件 V tt 良好
°
PL DDR3 SODIMM V tt 良好
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UG954 （v1.8） 2019 年 8 月 6 日
概述
°
FMC 电源正常
°
12V 输入开机
°
FPGA 初始化
°
FPGA 完成
•
用户 I/O：
°
四个 （PL） 用户 LED
°
三个 （PL） 用户按钮
°
一个 （PL） 用户 DIP 开关（4 极）
°
两个双排 Pmod GPIO 接头
•
SoC PS 复位按钮：
°
SRST_B PS 重置按钮
°
POR_B PS 重置按钮
•
VITA 57.1 FMC HPC 连接器
•
VITA 57.1 FMC LPC 连接器
•
电源开/关滑动开关
•
Program_B pushbutton
•
Power management with PMBus voltage and current monitoring through TI power controller
•
Dual 12-bit 1 MSPS XADC analog-to-digital front end
•
Configuration options:
°
Dual Quad-SPI flash memory
°
USB JTAG configuration port (Digilent module)
°
Platform cable header JTAG configuration port
°
20-pin PL PJTAG header
Send Feedback
ZC706 Evaluation Board User Guide www.xilinx.com
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UG954 (v1.8) August 6, 2019
Overview
Block Diagram
The ZC706 evaluation board block diagram is shown in Figure 1-1.
Board Layout
Figure 1-3 shows the ZC706 evaluation board. Each numbered feature that is referenced in Figure 1-3 is described in Table 1-1 with a link to detailed information provided under Feature Descriptions starting on page 15.
Note: The image in Figure 1-3 is for reference only and might not reflect the current revision of the board.
X-Ref Target - Figure 1-1
Figure 1-1: ZC706 Evaluation Board Block Diagram
U1
Zync-7000 AP SoC
XC7Z045-2FFG900C
Processing
System
Programmable Logic
UG954_c1_01_1002012
JTAG Module
and
JTAG Header Page 16
Dual Quad-SPI
Flash Memory
Page 21
PCIe
x 4-Lane
Page 42
SD Card
Connector
Page 22
FMC HPC
Connector
Pages 24-27
10/100/1,000
Ethernet PHY
(RGMII only) Page 29, 30
USB 2.0 ULPI
Transceiver
and Connector Page 31
Clock and
Reset/POR
Pushbuttons Pages 15, 34
USB UART
and
Connector Page 40
ARM PJTAG
页眉
第 39 页
开关
LED 和
按钮 第 38 页
机械
第 58 页
我 C
实时
时钟 第 37 页
DDR3 内存
SODIMM 系列
第 23 页
DDR3 内存
4 x 256 Mb x 8
SDRAM 第 17-20 页
HDMI 编解码器
和
连接页 32， 33
I C 多路复用器
和
IC EEPROM 第 36 页
XADC
页眉
第 35 页
配置
时钟
第 34 页
FMC LPC
连接器
第 28 页
注： 页码是指原理图 0381513 的页码。
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UG954 （v1.8） 2019 年 8 月 6 日
放电注意事项
放电注意事项
谨慎！如果处理不当，ESD 会损坏电子元件，并可能导致完全或间歇性故障。拆卸和更换组件时，请始终遵循 ESD 预防程序。
为防止 ESD 损坏：
•
使用 ESD 腕带或踝带，并确保它与皮肤接触。将腕带的设备端连接到机箱上未上漆的金属表面。
•
避免将适配器碰到您的衣服上。腕带仅保护元件免受本体上的 ESD 影响。
•
仅通过支架或边缘处理适配器。避免触摸印刷电路板或连接器。
•
仅将适配器放在防静电表面上，例如套件中提供的袋子。
•
如果您要将适配器退回 Xilinx 产品支持，请立即将其放回防静电袋中。
•
如果没有腕带，请在处理适配器或计算机/服务器的任何其他部件之前触摸金属机箱，将自己接地。
X-Ref Target - Figure 1-2
图 1-2：AC701 板框图
UG952_c1_01_101512
Artix-7 FPGA
XC7A200T-2FBG676C
128 Mb 四通道 SPI
闪存
SD 卡
接口
4 通道 PCI Express
边缘连接器
LCD 显示屏（2 行 x 16 个字符）
1 KB EEPROM （I2C）
I2C 总线开关
XADC 接头
用户开关，
按钮和 LED
HDMI 视频
接口
差分时钟
GTP SMA 时钟
1 GB DDR3 内存
（SODIMM）
FMC 连接器
（高性能计算）
10/100/1000 以太网
接口
拨码开关 SW1
配置
USB 转 UART 桥接器
JTAG 接口 micro-B USB 连接器
SFP+ 单壳体
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UG954 （v1.8） 2019 年 8 月 6 日
放电注意事项
X-Ref Target - Figure 1-3
图 1-3：ZC706 评估板组件位置
17
6
30
31
21
18
15
2
11
13
12
1
4
7
3
9
10
16
25
24
26
22
33
27
19
32
23
28
14
35
29
5
8
20
34
36 37
38
00
方形标注引用电路板背面的元件
圆形标注引用电路板正面的元件
00
UG954_c1_02_042114
表 1-1：ZC706 评估板组件说明
标注
特征
笔记
图解的
0381513
页码
1
Zynq-7000 XC7Z045 SoC，第 15 页带风扇接收器的 Zynq-7000 SoC
XC7Z045T-2FFG900C 带 Radian INC3001-7_1.5BU_LI98 风扇水槽
2
DDR3 SODIMM 内存 （PL），第 19 页 DDR3 SODIMM 内存插槽 （J1）
美光 MT8JTF12864HZ-1G6G1
23
3
DDR3 组件内存 （PS），第 23 页 DDR3 内存 1GB （4x256M U2-U5）
美光 MT41J256M8HX-15E
17-20
4
Quad-SPI 闪存，第 26 页双通道 Quad-SPI 闪存 （128Mb） （U58-U59）
跨度 S25FL128SAGMFIR01
21
5
SD 卡接口，第 31 页 SD 卡接口连接器 （J30）
莫仕 67840-8001
22
6
USB 2.0 ULPI 收发器，第 29 页 USB JTAG 接口，带 Micro-B 连接器 （U30）
Digilent USB JTAG 模块
16
7
系统时钟，第 36 页系统时钟，2.5V LVDS （U64）
西泰姆 SIT9102-243N25E200.0000
34
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UG954 （v1.8） 2019 年 8 月 6 日
放电注意事项
8
可编程用户时钟，第 37 页 I C Prog. 用户时钟 3.3V LVDS（U37，板底部）
Silicon Labs SI570BAB0000544DG，默认 156.250 MHz
34
9
用户 SMA 时钟源，第 38 页用户差分 SMA 时钟 P/N （J67/J68）
罗森伯格 32K10K-400L5
44
10
GTX SMA 时钟（SMA_MGT_REFCLK_P 和 SMA_MGT_REFCLK_N），第 39 页 GTX 差分 SMA 时钟 P/N （J36/J31）
罗森伯格 32K10K-400L5
44
11
抖动衰减时钟，第 40 页抖动衰减时钟（U60，板底部）
Silicon Labs SI5324C-C-GM
43
12
GTX 收发器，第 41 页 GTX 收发器
嵌入在 SoC U1 中
8
13
PCI Express 端点连接，第 46 页 PCI Express 连接器 （P4）
4 通道卡边缘连接器
42
14
SFP/SFP+ 模块连接器，第 48 页 SFP/SFP+ 模块连接器 （P2）
莫莱克斯 74441-0010
41
15
10/100/1000 Mb/s 三速以太网 PHY （PS），第 49 页仅 RGMII 10/100/1000 Mb/s 以太网 PHY 带 RJ45 （U51， P3）
美满 88E1116RA0-NNC1C000
29
16
GTX 差分 SMA TX 和 RX P/N（J35/J34 和 J32/J33）
罗森伯格 32K10K-400L5
44
17
USB 转 UART 桥接器，第 51 页带 Mini-B 连接器的 USB 转 UART 桥接器（U52、J21）
Silicon Labs CP2103GM 桥
40
18
HDMI 视频输出，第 52 页 HDMI 控制器 （U53），HDMI 视频连接器 （P1）
Analog Devices ADV7511KSTZ-P， Molex 500254-1927，
32, 33
19
USB 2.0 ULPI 收发器，第 29 页 USB 2.0 ULPI 控制器，带 Micro-B 连接器（U12、J2）
SMSC USB3320C-EZK
31
20
I2C 总线，第 55 页 I C 总线多路复用器（U65，板底部）
在 PCA9548ARGER
36
21
以太网 PHY 用户 LED，第 59 页以太网 PHY 状态 LED 指示灯 （DS28-DS30）
EPHY 状态 LED，绿色单堆栈
29
22
用户 LED，第 60 页 用户 LED（DS8-DS10、DS35）
GPIO LED，绿色 0603
38
23
用户按钮，第 61 页用户按钮，高电平有效（SW7、9、8）
左、中、右模式的 E-Switch TL3301EF100QG
38
表 1-1：ZC706 评估板组件说明（续）
标注
特征
笔记
图解的
0381513
页码
发送反馈
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UG954 （v1.8） 2019 年 8 月 6 日
放电注意事项
24
GPIO DIP 开关，第 62 页 GPIO DIP 开关 （SW12）
4-pole C&K SDA04H1SBD
38
25
ARM® core PJTAG Header (J64)
2x10 0.1inch male header, Samtec TST-110-01-G-D
39
26
User PMOD GPIO Headers, page 62 PMOD Headers (J57, J58)
2x6 0.1 inch male header
37, 39
27
Power On/Off Slide Switch, page 64 Power On/Off Switch (SW1)
C&K 1201M2S3AQE2
48
28
Program_B Pushbutton, page 65 FPGA PROG pushbutton (SW10)
E-Switch TL3301EF100QG
38
29
SoC MIO Config. DIP Switch (SW11)
5-pole DPDT CTS 206-125
15
30
HPC Connector J37, page 67 FMC HPC connector (J37)
Samtec ASP_134486_01
24-27
31
LPC Connector J5, page 71 FMC LPC connector (J5)
Samtec ASP_134603_01
28
32
Power Management, page 79 Power Management System (top and bottom of board)
TI UCD90120ARGC in conjunction w/various regulators
48-57
33
XADC Analog-to-Digital Converter, page 85 XADC Connector (J63)
2x10 0.1inch male header, Samtec TST-110-01-G-D
35
34
Programmable Logic JTAG Select Switch, page 33 JTAG Configuration DIP Switch (SW4)
2-pole C&K SDA02H1SBD
16
35
JTAG Flying Lead Header (J62)
2x10 0.1inch male header, Samtec TST-110-01-G-D
16
36
2x5 shrouded PMBus connector J4
ASSMAN HW10G-0202
48
37
2x7 2mm shrouded JTAG cable connector J3
MOLEX 87832-1420
16
38
12V power input 2x6 connector J22
MOLEX-39-30-1060
48
Notes:
1.
Jumper header locations are identified in Appendix A, Default Switch and Jumper Settings.
Table 1-1: ZC706 Evaluation Board Component Descriptions (Cont’d)
Callout
Feature
Notes
Schematic
0381513
Page Number
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Feature Descriptions
Detailed information for each feature shown in Figure 1-3 and listed in Table 1-1 is provided in this section.
Zynq-7000 XC7Z045 SoC
[Figure 1-3, callout 1]
The ZC706 evaluation board is populated with the Zynq-7000 XC7Z045-2FFG900C SoC.
The XC7Z045 SoC consists of an integrated processing system (PS) and programmable logic (PL), on a single die. The high-level block diagram is shown in Figure 1-4.
The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA® interconnect, internal memories, external memory interfaces, and peripherals including USB, Ethernet, SPI, SD/SDIO, I C , CAN, UART, and GPIO. The PS runs independently of the PL and boots at power-up or reset.
A system level block diagram is shown in Figure 1-5.
X-Ref Target - Figure 1-4
Figure 1-4: High-Level Block Diagram
Application Processor Unit (APU)
Common
Peripherals
Custom
Peripherals
Common Accelerators
Custom Accelerators
Memory
Interfaces
Processing
System
(PS)
Programmable
Logic
(PL)
Input Output
Peripherals
(IOP)
High-Bandwidth
AMBAAXI Interfaces
UG954_c1_03_100112
Interconnect
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
For additional information on Zynq-7000 SoC devices, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
Device Configuration
the Zynq-7000 XC7Z045 SoC uses a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC706 evaluation board supports these configuration options:
•
PS Configuration: Quad-SPI flash memory
•
PS Configuration: Processor System Boot from SD Card (J30)
X-Ref Target - Figure 1-5
Figure 1-5: Zynq-7000 Block Diagram
2x USB 2x GigE 2x SD
Zynq-7000 AP SoC
I/O
Peripherals
IRQ
IRQ
EMIO
SelectIO
Resources
DMA 8
Channel
CoreSight
Components
Programmable Logic
DAP
DevC
SWDT
DMA
Sync
Notes: 1) Arrow direction shows control (master to slave) 2) Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, Custom
ACP
256K
SRAM
Application Processor Unit
TTC
System-
Level
Control
Regs
GigE
CAN
SD
SDIO
UART
GPIO
UART
CAN
I2C
SRAM/
NOR ONFI 1.0
NAND
Processing System
Memory
Interfaces
Q-SPI
CTRL
USB
GigE
I2C
USB
SD
SDIO
SPI
SPI
Programmable Logic to Memory Interconnect
MMU
FPU and NEON Engine
Snoop Controller, AWDT, Timer
GIC
32 KB
I-Cache
ARM Cortex-A9
CPU
ARM Cortex-A9
CPU
MMU
FPU and NEON Engine
Config
AES/
SHA
XADC
12-Bit ADC
Memory
Interfaces
512 KB L2 Cache & Controller
OCM
Interconnect
DDR2/3,
LPDDR2
Controller
UG954_c1_04_100112
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
MIO
Clock
Generation
Reset
Central
Interconnect
General-Purpose
Ports
High-Performance Ports
Send Feedback
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Feature Descriptions
•
PL Configuration: USB JTAG configuration port (Digilent module U30)
•
PL Configuration: Platform cable header J3 and flying lead header J62 JTAG configuration ports
TIP: Designs using serial configuration based on Quad-SPI flash memory can take advantage of low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW11 (PS) as shown in Table 1-2 and SW4 (PL) as described in Programmable Logic JTAG Programming Options, page 33. SW11 is callout 29 in Figure 1-3.
For more information about Zynq-7000 SoC configuration settings, see Zynq-7000 SoC Technical Reference Manual (UG585).
Encryption Key Backup Circuit
The XC7Z045 SoC U1 implements bitstream encryption key technology. The ZC706 board provides the encryption key backup battery circuit shown in Figure 1-6. The Seiko TS518FE rechargeable 1.5V lithium button-type battery B2 is soldered to the board with the positive output connected to the XC7Z045 SoC U1 VCCBATT pin P9. The battery supply current IBATT specification is 150 nA max when board power is off. B2 is charged from the VCCAUX 1.8V rail through a series diode with a typical forward voltage drop of 0.38V and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.42V.
Table 1-2: Switch SW11 Configuration Option Settings
Boot Mode
SW11.1
SW11.2
SW11.3
SW11.4
SW11.5
JTAG mode
0
0
0
0
0
Independent JTAG mode
1
0
0
0
0
QSPI mode
0
0
0
1
0
SD mode
0
0
1
1
0
MIO configuration pin
MIO2
MIO3
MIO4
MIO5
MIO6
Notes:
1.
Default switch setting
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
I/O Voltage Rails
There are eleven I/O banks available on the XC7Z045 SoC. The voltages applied to the XC7Z045 SoC I/O banks used by the ZC706 evaluation board are listed in Table 1-3.
X-Ref Target - Figure 1-6
Figure 1-6: Encryption Key Backup Circuit
UG954_c1_05_041113
GND
2
1
B2
Lithium Battery
Seiko
TS518SE_FL35E
1.5V
2
1
3
BAS40-04
D7
40V 电压
200 毫瓦
数控
FPGA_VBATT
+
VCCAUX 餐厅
R9 系列
4.70K 1%
1/16 瓦
To XC7Z045 AP SoC
U1 引脚 P9
（VCCBATT）
表 1-3：I/O 电压轨 XC7Z045 （U1）
岸
网络名称
电压
连接到
PL Bank 0 （盈出库 0）
VCC3V3_FPGA
3.3V
SoC 配置库 0
PL Bank 9 （盈出银行 9）
VADJ_FPGA
2.5V
PMOD、USER_SMA_CLOCK、SM_FAN、REC_CLOCK SFP_TX_DISABLE
PL Bank 10 （盈方银行 10）
FMC_LPC、PL_JTAG、GPIO
PL Bank 11 （盈出银行 11）
FMC_HPC、GPIO_LED、HDMI
PL Bank 12 （盈方银行 12）
FMC_LPC、HDMI
PL Bank 13
FMC_HPC、HDMI
PL 银行 33
VCC1V5_PL
1.5V
PL_DDR3_D[31：0]
PL Bank 34
PL_DDR3_A、SYSCLK
PL Bank 35
PL_DDR3_D[63：32]， XADC
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UG954 （v1.8） 2019 年 8 月 6 日
功能描述
DDR3 SODIMM 内存 （PL）
[图 1-3，标注 2]
J1 的内存模块是 1 GB DDR3 小外形双列直插式内存模块 （SODIMM）。它提供易失性同步动态随机存取存储器 （SDRAM），用于存储用户代码和数据。
•
零件编号：MT8JTF12864HZ-1G6G1 （Micron Technology）
•
电源电压：1.5V
•
数据路径宽度：64 位
•
数据速率：高达 1,600 MT/s
ZC706 XC7Z045 SoC PL DDR 接口性能记录在 Zynq-7000 SoC（Z-7030、035、045 和 Z-7100）：直流和交流开关特性数据表 （DS191）[参考文献 2] 中。
DDR3 接口在 PL 侧 I/O bank 上实现。bank 33 和 bank 35 具有专用的 DCI VRP/N 电阻器连接。为数据接口组提供了一个外部 0.75V 基准 VTTREF_SODIMM。任何连接到这些 bank 的需要 VTTREF 电压的接口都必须使用此 FPGA 电压参考。DDR3 内存和 SoC 之间的连接如表 1-4 所示。
PS 银行 500
VCCP1V8
1.8V
QSPI0、QSPI1
PS 银行 501
PHY_IF，SDIO_IF，USB_IF
PS 银行 502
PS_DDR3_IF
笔记：
1.
ZC706 评估板出厂时 V 设置为 2.5V。
表 1-4：DDR3 SODIMM 插槽 J1 与 XC7Z045 SoC 的连接
XC7Z045 （U1）
针
网络名称
I/O 标准
DDR3 SODIMM 内存 J1
引脚号
引脚名称
E10 系列
PL_DDR3_A0
SSTL15
98
答 0
B9 系列
PL_DDR3_A1
SSTL15
97
答 1
E11 系列
PL_DDR3_A2
SSTL15
96
答 2
答 9
PL_DDR3_A3
SSTL15
95
答 3
D11
PL_DDR3_A4
SSTL15
92
A4
B6 系列
PL_DDR3_A5
SSTL15
91
答 5
F9 系列
PL_DDR3_A6
SSTL15
90
答 6
表 1-3：I/O 电压轨（续）
XC7Z045 （U1）
岸
网络名称
电压
连接到
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功能描述
E8 系列
PL_DDR3_A7
SSTL15
86
答 7
B10 系列
PL_DDR3_A8
SSTL15
89
答 8
D8
PL_DDR3_A9
SSTL15
85
答 9
D6 系列
PL_DDR3_A10
SSTL15
107
A10/AP
B7 系列
PL_DDR3_A11
SSTL15
84
答 11
H12 系列
PL_DDR3_A12
SSTL15
83
A12_BC_N
答 10
PL_DDR3_A13
SSTL15
119
答 13
11 年级
PL_DDR3_A14
SSTL15
80
答 14
C6 系列
PL_DDR3_A15
SSTL15
78
答 15
F8
PL_DDR3_BA0
SSTL15
109
BA0 系列
H7 系列
PL_DDR3_BA1
SSTL15
108
BA1 系列
答 7
PL_DDR3_BA2
SSTL15
79
BA2 系列
L1 系列
PL_DDR3_D0
SSTL15
5
DQ0
L2 （二层）
PL_DDR3_D1
SSTL15
7
DQ1
K5 系列
PL_DDR3_D2
SSTL15
15
DQ2
第 4 天
PL_DDR3_D3
SSTL15
17
DQ3
K1 （英语）
PL_DDR3_D4
SSTL15
4
DQ4
L3 系列
PL_DDR3_D5
SSTL15
6
DQ5
第 5 天
PL_DDR3_D6
SSTL15
16
DQ6
K6 系列
PL_DDR3_D7
SSTL15
18
DQ7
G6 系列
PL_DDR3_D8
SSTL15
21
DQ8
H4 系列
PL_DDR3_D9
SSTL15
23
DQ9
H6
PL_DDR3_D10
SSTL15
33
DQ10
H3
PL_DDR3_D11
SSTL15
35
DQ11
G1
PL_DDR3_D12
SSTL15
22
DQ12
H2
PL_DDR3_D13
SSTL15
24
DQ13
G5
PL_DDR3_D14
SSTL15
34
DQ14
G4
PL_DDR3_D15
SSTL15
36
DQ15
E2
PL_DDR3_D16
SSTL15
39
DQ16
E3
PL_DDR3_D17
SSTL15
41
DQ17
D4
PL_DDR3_D18
SSTL15
51
DQ18
E5
PL_DDR3_D19
SSTL15
53
DQ19
F4
PL_DDR3_D20
SSTL15
40
DQ20
F3
PL_DDR3_D21
SSTL15
42
DQ21 系列
第一天
PL_DDR3_D22
SSTL15
50
DQ22 系列
表 1-4：DDR3 SODIMM 插槽 J1 与 XC7Z045 SoC 的连接（续）
XC7Z045 （U1）
针
网络名称
I/O 标准
DDR3 SODIMM 内存 J1
引脚号
引脚名称
发送反馈
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功能描述
D3
PL_DDR3_D23
SSTL15
52
DQ23
答 2
PL_DDR3_D24
SSTL15
57
DQ24 系列
B2 层
PL_DDR3_D25
SSTL15
59
DQ25 系列
B4 厅
PL_DDR3_D26
SSTL15
67
DQ26
B5
PL_DDR3_D27
SSTL15
69
DQ27
A3
PL_DDR3_D28
SSTL15
56
DQ28
B1
PL_DDR3_D29
SSTL15
58
DQ29
C1
PL_DDR3_D30
SSTL15
68
DQ30
C4
PL_DDR3_D31
SSTL15
70
DQ31
K10
PL_DDR3_D32
SSTL15
129
DQ32
L9
PL_DDR3_D33
SSTL15
131
DQ33
K12
PL_DDR3_D34
SSTL15
141
DQ34
J9
PL_DDR3_D35
SSTL15
143
DQ35
K11
PL_DDR3_D36
SSTL15
130
DQ36
L10
PL_DDR3_D37
SSTL15
132
DQ37
J10
PL_DDR3_D38
SSTL15
140
DQ38
L7
PL_DDR3_D39
SSTL15
142
DQ39
F14
PL_DDR3_D40
SSTL15
147
DQ40
F15
PL_DDR3_D41
SSTL15
149
DQ41
F13
PL_DDR3_D42
SSTL15
157
DQ42
G16
PL_DDR3_D43
SSTL15
159
DQ43
G15
PL_DDR3_D44
SSTL15
146
DQ44
E12
PL_DDR3_D45
SSTL15
148
DQ45
D13
PL_DDR3_D46
SSTL15
158
DQ46
E13
PL_DDR3_D47
SSTL15
160
DQ47
D15
PL_DDR3_D48
SSTL15
163
DQ48
E15
PL_DDR3_D49
SSTL15
165
DQ49
D16
PL_DDR3_D50
SSTL15
175
DQ50
E16
PL_DDR3_D51
SSTL15
177
DQ51
C17
PL_DDR3_D52
SSTL15
164
DQ52
B16
PL_DDR3_D53
SSTL15
166
DQ53
D14
PL_DDR3_D54
SSTL15
174
DQ54
B17
PL_DDR3_D55
SSTL15
176
DQ55
B12
PL_DDR3_D56
SSTL15
181
DQ56
C12
PL_DDR3_D57
SSTL15
183
DQ57
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont’d)
XC7Z045 (U1)
Pin
Net Name
I/O Standard
DDR3 SODIMM Memory J1
Pin Number
Pin Name
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UG954 (v1.8) August 6, 2019
Feature Descriptions
A12
PL_DDR3_D58
SSTL15
191
DQ58
A14
PL_DDR3_D59
SSTL15
193
DQ59
A13
PL_DDR3_D60
SSTL15
180
DQ60
B11
PL_DDR3_D61
SSTL15
182
DQ61
C14
PL_DDR3_D62
SSTL15
192
DQ62
B14
PL_DDR3_D63
SSTL15
194
DQ63
J3
PL_DDR3_DM0
SSTL15
11
DM0
F2
PL_DDR3_DM1
SSTL15
28
DM1
E1
PL_DDR3_DM2
SSTL15
46
DM2
C2
PL_DDR3_DM3
SSTL15
63
DM3
L12
PL_DDR3_DM4
SSTL15
136
DM4
G14
PL_DDR3_DM5
SSTL15
153
DM5
C16
PL_DDR3_DM6
SSTL15
170
DM6
C11
PL_DDR3_DM7
SSTL15
187
DM7
K2
PL_DDR3_DQS0_N
DIFF_SSTL15
10
DQS0_N
K3
PL_DDR3_DQS0_P
DIFF_SSTL15
12
DQS0_P
H1
PL_DDR3_DQS1_N
DIFF_SSTL15
27
DQS1_N
J1
PL_DDR3_DQS1_P
DIFF_SSTL15
29
DQS1_P
D5
PL_DDR3_DQS2_N
DIFF_SSTL15
45
DQS2_N
E6
PL_DDR3_DQS2_P
DIFF_SSTL15
47
DQS2_P
A4
PL_DDR3_DQS3_N
DIFF_SSTL15
62
DQS3_N
A5
PL_DDR3_DQS3_P
DIFF_SSTL15
64
DQS3_P
K8
PL_DDR3_DQS4_N
DIFF_SSTL15
135
DQS4_N
L8
PL_DDR3_DQS4_P
DIFF_SSTL15
137
DQS4_P
F12
PL_DDR3_DQS5_N
DIFF_SSTL15
152
DQS5_N
G12
PL_DDR3_DQS5_P
DIFF_SSTL15
154
DQS5_P
E17
PL_DDR3_DQS6_N
DIFF_SSTL15
169
DQS6_N
F17
PL_DDR3_DQS6_P
DIFF_SSTL15
171
DQS6_P
A15
PL_DDR3_DQS7_N
DIFF_SSTL15
186
DQS7_N
B15
PL_DDR3_DQS7_P
DIFF_SSTL15
188
DQS7_P
G7
PL_DDR3_ODT0
SSTL15
116
ODT0
C9
PL_DDR3_ODT1
SSTL15
120
ODT1
G17
PL_DDR3_RESET_B
SSTL15
30
RESET_B
J11
PL_DDR3_S0_B
SSTL15
114
S0_B
H8
PL_DDR3_S1_B
SSTL15
121
S1_B
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont’d)
XC7Z045 (U1)
Pin
Net Name
I/O Standard
DDR3 SODIMM Memory J1
Pin Number
Pin Name
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
The ZC706 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the “Dynamic Memory” section of the Zynq-7000 SoC PCB Design and Pin Planning Guide
(UG933). The ZC706 DDR3 SODIMM interface is a 40Ω impedance implementation. For more details, see the MT8JTF12864HZ-1G6G1 data sheet [Ref 35].
DDR3 Component Memory (PS)
[Figure 1-3, callout 3]
The 1 GB, 32-bit wide DDR3 component memory system is comprised of four SDRAMs at U2-U5. This memory system is connected to the XC7Z045 SoC Processing System (PS) memory interface bank 502.
•
Part number: MT41J256M8HX-15E (Micron Technology)
•
Configuration: 2Gb: 256 Mb x 8
•
Supply voltage: 1.5V
•
Datapath width: 32 bits
•
Data rate: Up to 1,333 MT/s
The ZC706 XC7Z045 SoC PS DDR Bank 502 interface performance is documented in the Zynq-7000 SoC (Z-7030, 035, 045, and Z-7100): DC and AC Switching Characteristics Data Sheet (DS191)[Ref 2].
The DDR3 0.75V VTT termination voltage is sourced from linear regulator U27. The connections between the DDR3 component memory and XC7Z045 SoC bank 502 are listed in Table 1-5.
M10
PL_DDR3_TEMP_EVE
NT
SSTL15
198
EVENT_B
F7
PL_DDR3_WE_B
SSTL15
113
WE_B
E7
PL_DDR3_CAS_B
SSTL15
115
CAS_B
H11
PL_DDR3_RAS_B
SSTL15
110
RAS_B
D10
PL_DDR3_CKE0
SSTL15
73
CKE0
C7
PL_DDR3_CKE1
SSTL15
74
CKE1
F10
PL_DDR3_CLK0_N
DIFF_SSTL15
103
CK0_N
G10
PL_DDR3_CLK0_P
DIFF_SSTL15
101
CK0_P
D8
PL_DDR3_CLK1_N
DIFF_SSTL15
104
CK1_N
D9
PL_DDR3_CLK1_P
DIFF_SSTL15
102
CK1_P
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 SoC (Cont’d)
XC7Z045 (U1)
Pin
Net Name
I/O Standard
DDR3 SODIMM Memory J1
Pin Number
Pin Name
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-5: DDR3 Component Memory Connections to the XC7Z045 SoC
XC7Z045 (U1) Pin
Net Name
Component Memory
Pin Number
Pin Name
Ref. Des.
E26
PS_DDR3_DQ0
B3
DQ0
U2
A25
PS_DDR3_DQ1
C7
DQ1
U2
E27
PS_DDR3_DQ2
C2
DQ2
U2
E25
PS_DDR3_DQ3
C8
DQ3
U2
D26
PS_DDR3_DQ4
E3
DQ4
U2
B25
PS_DDR3_DQ5
E8
DQ5
U2
D25
PS_DDR3_DQ6
D2
DQ6
U2
B27
PS_DDR3_DQ7
E7
DQ7
U2
A27
PS_DDR3_DQ8
B3
DQ8
U3
A28
PS_DDR3_DQ9
C7
DQ9
U3
A29
PS_DDR3_DQ10
C2
DQ10
U3
C28
PS_DDR3_DQ11
C8
DQ11
U3
D30
PS_DDR3_DQ12
E3
DQ12
U3
A30
PS_DDR3_DQ13
E8
DQ13
U3
D29
PS_DDR3_DQ14
D2
DQ14
U3
D28
PS_DDR3_DQ15
E7
DQ15
U3
H27
PS_DDR3_DQ16
B3
DQ16
U4
G27
PS_DDR3_DQ17
C7
DQ17
U4
H28
PS_DDR3_DQ18
C2
DQ18
U4
E28
PS_DDR3_DQ19
C8
DQ19
U4
E30
PS_DDR3_DQ20
E3
DQ20
U4
F28
PS_DDR3_DQ21
E8
DQ21
U4
G30
PS_DDR3_DQ22
D2
DQ22
U4
F30
PS_DDR3_DQ23
E7
DQ23
U4
K27
PS_DDR3_DQ24
B3
DQ24
U5
J30
PS_DDR3_DQ25
C7
DQ25
U5
J28
PS_DDR3_DQ26
C2
DQ26
U5
J29
PS_DDR3_DQ27
C8
DQ27
U5
K30
PS_DDR3_DQ28
E3
DQ28
U5
M29
PS_DDR3_DQ29
E8
DQ29
U5
L30
PS_DDR3_DQ30
D2
DQ30
U5
M30
PS_DDR3_DQ31
E7
DQ31
U5
C27
PS_DDR3_DM0
B7
DM0
U2
C26
PS_DDR3_DQS0_P
C3
DQS0_P
U2
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
B26
PS_DDR3_DQS0_N
D3
DQS0_N
U2
B30
PS_DDR3_DM1
B7
DM1
U3
C29
PS_DDR3_DQS1_P
C3
DQS1_P
U3
B29
PS_DDR3_DQS1_N
D3
DQS1_N
U3
H29
PS_DDR3_DM2
B7
DM2
U4
G29
PS_DDR3_DQS2_P
C3
DQS2_P
U4
F29
PS_DDR3_DQS2_N
D3
DQS2_N
U4
K28
PS_DDR3_DM3
B7
DM3
U5
L28
PS_DDR3_DQS3_P
C3
DQS3_P
U5
L29
PS_DDR3_DQS3_N
D3
DQS3_N
U5
L25
PS_DDR3_A0
K3
A0
U2, U3, U4, U5
K26
PS_DDR3_A1
L7
A1
U2, U3, U4, U5
L27
PS_DDR3_A2
L3
A2
U2, U3, U4, U5
G25
PS_DDR3_A3
K2
A3
U2, U3, U4, U5
J26
PS_DDR3_A4
L8
A4
U2, U3, U4, U5
G24
PS_DDR3_A5
L2
A5
U2, U3, U4, U5
H26
PS_DDR3_A6
M8
A6
U2, U3, U4, U5
K22
PS_DDR3_A7
M2
A7
U2, U3, U4, U5
F27
PS_DDR3_A8
N8
A8
U2, U3, U4, U5
J23
PS_DDR3_A9
M3
A9
U2, U3, U4, U5
G26
PS_DDR3_A10
H7
A10
U2, U3, U4, U5
H24
PS_DDR3_A11
M7
A11
U2, U3, U4, U5
K23
PS_DDR3_A12
K7
A12
U2, U3, U4, U5
H23
PS_DDR3_A13
N3
A13
U2, U3, U4, U5
J24
PS_DDR3_A14
N7
A14
U2, U3, U4, U5
M27
PS_DDR3_BA0
J2
BA0
U2, U3, U4, U5
M26
PS_DDR3_BA1
K8
BA1
U2, U3, U4, U5
M25
PS_DDR3_BA2
J3
BA2
U2, U3, U4, U5
K25
PS_DDR3_CLK_P
F7
CK
U2, U3, U4, U5
J25
PS_DDR3_CLK_N
G7
CK_B
U2, U3, U4, U5
M22
PS_DDR3_CKE
G9
CKE
U2, U3, U4, U5
N23
PS_DDR3_WE_B
H3
WE_B
U2, U3, U4, U5
M24
PS_DDR3_CAS_B
G3
CAS_B
U2, U3, U4, U5
N24
PS_DDR3_RAS_B
F3
RAS_B
U2, U3, U4, U5
F25
PS_DDR3_RESET_B
N2
RESET_B
U2, U3, U4, U5
Table 1-5: DDR3 Component Memory Connections to the XC7Z045 SoC (Cont’d)
XC7Z045 (U1) Pin
Net Name
Component Memory
Pin Number
Pin Name
Ref. Des.
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
The ZC706 DDR3 component interface adheres to the constraints guidelines documented in
the DDR3 Design Guidelines section of Zynq-7000 SoC PCB Design and Pin Planning Guide
(UG933). The ZC706 DDR3 component interface is a 40Ω impedance implementation. For more details, see the MT41J256M8HX-15E data sheet [Ref 35].
Quad-SPI Flash Memory
[Figure 1-3, callout 4]
The Quad-SPI flash memory located at U58 and U59 provides 2 x 128 Mb of nonvolatile storage that can be used for configuration and data storage.
•
Part number: S25FL128SAGMFIR01 (Spansion)
•
Supply voltage: 1.8V
•
Datapath width: 4 bits
•
Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z045 SoC are listed in Table 1-6.
N22
PS_DDR3_CS_B
H2
CS_B
U2, U3, U4, U5
L23
PS_DDR3_ODT
G1
ODT
U2, U3, U4, U5
N21
PS_VRN
M21
PS_VRP
L22
VTTVREF_PS
L24
VTTVREF_PS
Table 1-5: DDR3 Component Memory Connections to the XC7Z045 SoC (Cont’d)
XC7Z045 (U1) Pin
Net Name
Component Memory
Pin Number
Pin Name
Ref. Des.
Table 1-6: Quad-SPI Flash Memory Connections to the XC7Z045 SoC
XC7Z045 (U1)
Schematic
Net Name
Quad-SPI Flash Memory
QSPI Device
MIO Select
Header
Pin Name
Bank
Pin Number
Pin Number
Pin Name
Ref. Des.
PS_MIO6
500
D24
QSPI0_CLK
16
C
U58
J74.2
PS_MIO5
500
C24
QSPI0_IO3
1
DQ3_HOLD_B
U58
J73.2
PS_MIO4
500
E23
QSPI0_IO2
9
WP_B
U58
J72.2
PS_MIO3
500
C23
QSPI0_IO1
8
DQ1
U58
J71.2
PS_MIO2
500
F23
QSPI0_IO0
15
DQ0
U58
J70.2
PS_MIO1
500
D23
QSPI0_CS_B
7
S_B
U58
N/A
PS_MIO9
500
A24
QSPI1_CLK
16
C
U59
N/A
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
The configuration section of the Zynq-7000 SoC Technical Reference Manual UG585, provides details on using the Quad-SPI flash memory.
Figure 1-7 shows the connections of the linear Quad-SPI flash memory on the ZC706 evaluation board. For more details, see the Spansion S25FL128SAGMFIR01 data sheet [Ref 17].
PS_MIO13
500
F22
QSPI1_IO3
1
DQ3_HOLD_B
U59
N/A
PS_MIO12
500
E21
QSPI1_IO2
9
WP_B
U59
N/A
PS_MIO11
500
A23
QSPI1_IO1
8
DQ1
U59
N/A
PS_MIO10
500
E22
QSPI1_IO0
15
DQ0
U59
N/A
PS_MIO0
500
F24
QSPI1_CS_B
7
S_B
U59
N/A
Table 1-6: Quad-SPI Flash Memory Connections to the XC7Z045 SoC (Cont’d)
XC7Z045 (U1)
Schematic
Net Name
Quad-SPI Flash Memory
QSPI Device
MIO Select
Header
Pin Name
Bank
Pin Number
Pin Number
Pin Name
Ref. Des.
Send Feedback
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Feature Descriptions
X-Ref Target - Figure 1-7
Figure 1-7: 128 Mb Quad-SPI Flash Memory
DQ3_HOLD_B
VCC
NC0
NC1
NC2
NC3
S_B
DQ1
C714
0.1UF
25V
X5R
C
DQ0
NC7
NC6
NC5
NC4
VSS
DQ2_VPP_WP_B
16
15
14
13
12
11
10
9
QSPI0_IO3
QSPI0_CS_B
QSPI0_IO1
QSPI0_CLK
QSPI0_IO0
QSPI0_IO2
QSPI1_IO3
QSPI1_CS_B
QSPI1_IO1
QSPI1_CLK
QSPI1_IO0
QSPI1_IO2
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
SO16_50P300X413
U58
GND
S25FL128SAGMFIR01
DQ3_HOLD_B
VCC
NC0
NC1
NC2
NC3
S_B
DQ1
C
DQ0
NC7
NC6
NC5
NC4
VSS
DQ2_VPP_WP_B
16
15
14
13
12
11
10
9
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
SO16_50P300X413
U59
GND
UG954_c1_06_073013
GND
VCCP1V8
VCC3V3_PS
VCCP1V8
VCCP1V8
VCC3V3_PS
VCCP1V8
1
2
C39
0.1UF
25V
X5R
GND
1
2
R207
330
1/10W
5%
1
2
R527
DNP
DNP
DNP
1
2
R531
0
1/10W
5%
1
2
R528
DNP
DNP
DNP
1
2
C715
0.1UF
25V
X5R
1 2
C40
0.1UF
25V
X5R
1
2
R208
330
1/10W
5%
1
2
R530
DNP
DNP
DNP
1
2
R532
0
1/10W
5%
1
2
R529
DNP
DNP
DNP
1
2
S25FL128SAGMFIR01
Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
USB 2.0 ULPI Transceiver
[Figure 1-3, callout 19]
The ZC706 evaluation board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI Transceiver at U12 to support a USB connection to the host computer. A USB cable is supplied in the ZC706 evaluation kit (Standard-A connector to host computer, Micro-B connector to ZC706 evaluation board connector J2). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device which drives the physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal. Consult the SMSC USB3320 data sheet for clocking mode details [Ref 18].
The interface to the USB3320 transceiver is implemented through the IP in the XC7Z045 SoC Processor System.
Table 1-7 describes the jumper settings for the USB 2.0 circuit. Bold text identifies the default OTG mode settings.
Table 1-7: USB Jumper Settings
Header
Function
Shunt Position
Notes
J11
USB PHY reset
Shunt ON = USB PHY reset
Shunt OFF = USB PHY normal operation
Clean reset requires external debouncing
J10
V 5V Supply Shunt ON = Host or OTG mode
Shunt OFF = Device mode
J48
RVBUS select
Position 1–2 = Device mode only (10 KΩ)
Position 2–3 = OTG or Host mode (1 KΩ)
Overvoltage protection
J50
CVBUS select
Position 1-2 = OTG and Device mode 1 μF
Position 2-3 = Host mode 120 μF
V load capacitance
J49
Cable ID select
Position 1-2 = A/B cable detect
Position 2-3 = ID not used
Used in OTG mode
J51
USB Micro-B
Position 1-2 = Shield connected to GND
Position 2-3 = Shield floating
Send Feedback
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Feature Descriptions
The connections between the USB Micro-B connector at J2 and the PHY at U12 are listed in Table 1-8.
The connections between the USB 2.0 PHY at U12 and the XC7Z045 SoC are listed in Table 1-9.
For additional information on the Zynq-7000 SoC device USB controllers, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
Table 1-8: USB Connector Pin Assignments and Signal Definitions Between J2 and U12
USB Connector
J1
Net Name
Description
USB3320 (U12)
Pin
Pin
Name
1
VBUS
USB_VBUS_SEL
+5V from host system
22
2
D_N
USB_D_N
Bidirectional differential serial data (N-side)
19
3
D_P
USB_D_P
Bidirectional differential serial data (P-side)
18
5
GND
GND
Signal ground
33
Table 1-9: USB 2.0 ULPI Transceiver Connections to the XC7Z045 SoC
XC7Z045 (U1)
Schematic Net Name
USB3320 (U12) Pin
Pin Name
Bank
Pin Number
PS_MIO36
501
H17
USB_CLKOUT
1
PS_MIO31
501
H21
USB_NXT
2
PS_MIO32
501
K17
USB_DATA0
3
PS_MIO33
501
G22
USB_DATA1
4
PS_MIO34
501
K18
USB_DATA2
5
PS_MIO35
501
G21
USB_DATA3
6
PS_MIO28
501
L17
USB_DATA4
7
PS_MIO37
501
B21
USB_DATA5
9
PS_MIO38
501
A20
USB_DATA6
10
PS_MIO39
501
F18
USB_DATA7
13
PS_MIO30
501
L18
USB_STP
29
PS_MIO29
501
E8
USB_DIR
31
PS_MIO7
500
D5
USB_RESET_B_AND
27 (via AND gate U13) Send Feedback
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Figure 1-8 shows the USB 2.0 ULPI transceiver circuitry. Note that the shield for the USB Micro-B connector (J2) can be tied to GND by a jumper on header J51 pins 1–2 (default). The USB shield can optionally be connected through a capacitor to GND by installing a capacitor (body size 0402) at location C335 and jumping pins 2-3 on header J51.
SD Card Interface
[Figure 1-3, callout 5]
The ZC706 evaluation board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. Information for the SD I/O card specification can be found at the SanDisk and SD card websites [Ref 19], [Ref 20].
The SDIO signals are connected to XC7Z045 SoC PS bank 501 which has its VCCMIO set to 1.8V. A MAX13035E high-speed logic-level translator (U11) is used between XC7Z045 SoC 1.8V PS bank 501 and the 3.3V SD card connector (J30).
X-Ref Target - Figure 1-8
Figure 1-8: USB 2.0 ULPI Transceiver
EN
OUT2
IN
GND
NC1
FLG
NC2
OUT1
REFSEL2_14
DATA0_3
RBIAS_23
ID_23
VBUS_22
VBAT_21
VDD33_P
DM_19
DP_18
CPEN33_17
NC_12
REFSEL0_8
DATA4_7
DATA6_10
CLKOUT_1
NXT_2
DATA2_5
REFSEL1_11
VDDIO_32
DIR_31
DATA5_9
DATA7_13
DATA1_4
SPK_L_15
REFCLK_26
SPK_R_16
XO_25
VDD18_30
DATA3_6
STP_29
VDD18_28RESETB_27
CTR_GND_33
SHLD5SHLD6
GND
SHLD4
VBUS
D_N
D_P
SHLD1SHLD2SHLD3
ID
1-2 = DEVICE MODE
OFF = DEVICE MODE
2-3 = HOST OR OTG MODE
ON = HOST OR OTG MODE
USB HOST POWER
1-2 = A/B CABLE DETECT
2-3 = ID NOT USED
3 PLACES
2 PLACES
CVBUS Select:
1-2: OTG Mode
2-3: Host Mode
1
2
L11
FERRITE-220
USB_D_P
27
USB_D_N
27
USB_RESET_B
31
USB_STP
9
USB_DIR
9
USB_DATA7
8
USB_DATA6
8
USB_DATA5
8
USB_DATA4
8
1
2
C76 0.1UF
25V
31
USB_D_N
2
1
R267
10.0K
1/10W
GND
1
2
J10
1
2
C380 1UF
16V
X5R
1011
5
9
1
2
3
678
4
J2
ZX62D_AB_5P8
GND
GND
1
2
C484 120UF
20V
TANT
3
2
1
J50
GND
1
2
3
J49
USB_CLKOUT
8
USB_NXT
8
USB_DATA1
8
USB_DATA0
8
USB_DATA2
8 USB_DATA3
8
14
3
24
23
22
21
20
19
18
17
12
8
7
10
1
2
5
11
32
31
9
13
4
15
26
16
25
30
6
29
28
27
33
U12 USB3320_QFN32
USB3320_QFN32
GND
1
2
C71
1
2
C70
0.1UF
25V
2
1
C496
18PF
50V
NPO
GND
GND
2
1
X2
24.000MHZ
GND
2
1
C209 2.2UF
6.3V
GND
GND
VCC5V0
GND
2
1
C335
DNP
1
2
3 J48
USB_VBUS_SEL
VCC5V0
2
1
C447
5.6UF
10V
1
2
L12
FERRITE-220
VCC3V3
GND
2
1
DS25
LED-RED-SMT
2
1
R389
261
1/10W
1
8
7
3
4
2
5
6
U22 SOP127P500X600_8
MIC2025_SOP8
2
1 R359 1.00K
1/16W
GND
1
2
C75 0.1UF
25V
USB_VBUS_SEL
1
2
3
J51
1
2
C469 150UF
10V
TANT
GND
2
1
C497 18PF
50V
NPO
2
1
R403
1.0M
1/10W
5%
1
2
C74
USB_ID
27
USB_VDD33
27
USB_ID
31
USB_D_P
31
NC
NC
NCNC
NC
USB_VDD33
27
GND
2
1
R1788.06K1%
2
1
25V
0.1UF
C72
VCCMIO
VCCP1V8
UG954_c1_07_041113
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Figure 1-9 shows the connections of the SD card interface on the ZC706 evaluation board.
Table 1-10 lists the SD card interface connections to the XC7Z045 SoC
X-Ref Target - Figure 1-9
Figure 1-9: SD Card Interface
UG954_c1_08_041113
GND
GND
GND
IOGND2
GNDTAB1
GNDTAB2
GNDTAB3
CMD
VSS1
CLK
VSS2
DAT0
DAT1
DAT2
CD_DAT3
DETECT
VDD
PROTECT
DETECT_PROTECT
GNDTAB4
IOGND1
SDIO_SDWP
8
SDIO_SDDET
8
1
2
5%
1/10W
4.7 KΩ
R29
2
1
R28
4.7 KΩ
1/10W
5%
VCCP1V8
18
13
14
15
2
3
5
6
7
8
9
1
10
4
11
12
16
17
J30
67840-8001
22
SDIO_CLK
VCC3V3_PS
1
2
C41
0.1 μF
25V
X5R
SDIO_DAT2
22
SDIO_DAT0
22
22
SDIO_DAT1
SDIO_CD_DAT3
22
22
SDIO_CMD
Table 1-10: SDIO Connections to the XC7Z045 SoC
XC7Z045 (U1) Pin
Schematic
Net Name
Level Shifter (U11)
SDIO Connector (J30)
Pin Name
Bank
Pin
Number
1.8V Side
Pin
3.3V Side
Pin
Pin
Number
Pin
Name
PS_MIO15
500
C22
SDIO_SDWP
N/A
N/A
11
PROTECT
PS_MIO14
500
B22
SDIO_SDDET
N/A
N/A
10
DETECT
PS_MIO41
501
J18
SDIO_CMD_LS
4
20
2
CMD
PS_MIO40
501
B20
SDIO_CLK_LS
9
19
5
CLK
PS_MIO44
501
E20
SDIO_DAT2_LS
1
23
9
DAT2
PS_MIO43
501
E18
SDIO_DAT1_LS
7
16
8
DAT1
PS_MIO42
501
D20
SDIO_DAT0_LS
6
18
7
DAT0
PS_MIO45
501
H18
SDIO_CD_DAT3_LS
3
22
1
CD_DAT3
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Programmable Logic JTAG Programming Options
[Figure 1-3, callout 6]
The ZC706 evaluation board JTAG chain is shown in Figure 1-10.
Programmable Logic JTAG Select Switch
[Figure 1-3, callout 35]
The PL JTAG chain can be programmed by three different methods made available through a 3-to-1 analog switch (U45, U46, and U47) controlled by a 2-position DIP switch at SW4.
Figure 1-11 shows the JTAG analog switches and DIP switch SW4.
X-Ref Target - Figure 1-10
Figure 1-10: JTAG Chain Block Diagram
UG954_c1_09_041113
3.3V
3.3V
FMC HPC
Connector
TDI TDO
J37
U1
Zynq-7000
XC7Z045
AP SoC
TDI
TDO
SN74AVC2T245
and
SN74LV541APWR
Buffers TDI
TDO
U10
FMC LPC
Connector
TDI TDO
J5
SPST Bus Switch
U32
N.C.
N.C.
SPST Bus Switch
U31
JTAG
Module TDO
TDI
U30
JTAG
Header
TDO
TDI
J3
JTAG
Header TDO
TDI
J62
3:1
Analog
Switch
U45
U46
U47
SW4
1
2
ON
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UG954 (v1.8) August 6, 2019
Feature Descriptions
DIP switch SW4[1:2] setting 10 selects the 14-pin header J3 for configuration using either a Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW4 setting 01 selects the USB-to-JTAG Digilent bridge U30 for configuration over a Standard-A to Micro-B USB cable. DIP switch SW4 setting 11 selects the JTAG 20-pin header at J62. The four JTAG signals TDI, TDO, TCK, and TMS would be connected to J62 through flying leads from a JTAG cable. The 3-to-1 analog switch settings are shown in Table 1-11.
X-Ref Target - Figure 1-11
Figure 1-11: PL JTAG Programming Source Analog Switch
UG954_c1_10_041113
SDA02H1SBD
SW4
VCC3V3
4
3
JTAG_SEL_1
JTAG_SEL_2
R20
4.7kΩ
0.1 W
5%
R21
4.7kΩ
0.1 W
5%
GND
1
2
JTAG_TCK
U47
TS5A3359
SP3T
ANALOG SWITCH
1
2
3
4
GND
8
6
5
7
IN2
IN1
V+
U46
TS5A3359
SP3T
ANALOG SWITCH
1
2
3
4
GND
8
6
5
7
IN2
IN1
V+
U45
TS5A3359
SP3T
ANALOG SWITCH
1
2
3
4
GND
8
6
5
7
IN2
IN1
V+
NO1
NO2
NO0
COM
NO1 NO2
NO0
COM
NO1
NO2
NO0
COM
VCC3V3
JTAG_TMS
JTAG_TDI
14PIN_JTAG_TCK
14PIN_JTAG_TDI
14PIN_JTAG_TMS
DIGILENT_TCK
DIGILENT_TMS
DIGILENT_TDI
20PIN_JTAG_TCK
20PIN_JTAG_TMS
20PIN_JTAG_TDI
To J3
Parallel Cable or
Platform Cable
(14 pins)
To U30
USB-to-JTAG
Digilent bridge
To J62
Parallel Cable
(20 Pins)
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UG954 (v1.8) August 6, 2019
Feature Descriptions
FMC Connector JTAG Bypass
When an FPGA mezzanine card (FMC) is attached to HPC J37 or LPC J5 it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U32 and U31 respectively. The SPST switches are normally closed and transition to an open state when an FMC is attached. Switch U32 adds an attached FMC to the JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal. Switch U31 adds an attached FMC to the JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO connection through a device or bypass jumper for the JTAG chain to be completed to the SoC U1.
The JTAG connectivity on the ZC706 board allows a host computer to download bitstreams to the SoC using the Xilinx® iMPACT software. In addition, the JTAG connector allows debug tools such as the Vivado serial I/O analyzer or a software debugger to access the SoC. The iMPACT software tool can also indirectly program the linear QSPI flash memory. To accomplish this, the iMPACT software configures the SoC with a temporary design to access and program the QSPI memory device.
Clock Generation
[Figure 1-3, callouts 7, 8, and 9]
The ZC706 evaluation board provides four clock sources for the XC7Z045 SoC. Table 1-12 lists the source devices for each clock.
Table 1-11: Switch SW4 Configuration Option Settings
Configuration Source
DIP Switch SW4
Switch 1 JTAG_SEL_1
Switch 2 JTAG_SEL_2
None
0
0
Cable Connector J3(2)
1
0
Digilent USB-to-JTAG interface U30
0
1
JTAG (flying lead) Header J62
1
1
Notes:
1.
0 = open, 1 = closed
2.
Default switch setting
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-13 lists the pin-to-pin connections from each clock source to the XC7Z045 SoC.
System Clock
[Figure 1-3, callout 7]
Table 1-12: ZC706 Evaluation Board Clock Sources
Clock Name
Clock Source
Description
System Clock
U64
SiT9102 2.5V LVDS 200 MHz fixed-frequency oscillator (SiTime).
See System Clock, page 36.
User Clock
U37
Si570 3.3V LVDS I C programmable oscillator, 156.250 MHz default (Silicon Labs). See Programmable User Clock, page 37.
User SMA Clock
J67(P), J68(N)
User clock input SMAs, limit input swing voltage to VADJ_FPGA setting (1.8V, 2.5V, 3.3V). See User SMA Clock Source, page 38.
PS Clock
U24
SIT8103 1.8V single-ended CMOS 33.3333 MHz fixed frequency oscillator (SiTime). See Processing System Clock Source, page 39.
GTX SMA REF Clock
J36(P), J31(N)
User clock input SMAs. See GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N), page 39.
Jitter Attenuated Clock
U60
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs).
See Jitter Attenuated Clock, page 40.
Table 1-13: Clock Connections, Source to XC7Z045 SoC
Clock Source Pin
Net Name
I/O Standard
XC7Z045 (U1) Pin
U64.5
SYSCLK_N
LVDS
G9
U64.4
SYSCLK_P
LVDS
H9
U37.5
USRCLK_N
LVDS_25
AG14
U37.4
USRCLK_P
LVDS_25
AF14
J67.1
USER_SMA_CLOCK_P
LVDS_25
AD18
J68.1
USER_SMA_CLOCK_N
LVDS_25
AD19
J24.3
PS_CLK
NA(1)
A22 (Bank 500)
J36.1
SMA_MGT_REFCLK_P
NA(1)
W8
J31.1
SMA_MGT_REFCLK_N
NA(1)
W7
U60.29
SI5324_OUT_C_N
NA(1)
AC7
U60.28
SI5324_OUT_C_P
NA(1)
AC8
U60.17
REC_CLOCK_C_N
LVDS_25
AE20
U60.16
REC_CLOCK_C_P
LVDS_25
AD20
U60.3
SI5324_INT_ALM_LS
LVCMOS25
AJ25
U60.1
SI5324_RST_LS
LVCMOS25
W23
Notes:
1.
PS-side and GTX nets do not have an assigned I/O standard.
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UG954 (v1.8) August 6, 2019
Feature Descriptions
The system clock source is an LVDS 200 MHz oscillator at U64. It is wired to a multi-region clock capable (MRCC) input on programmable logic (PL) bank 34. The signal pair is named SYSCLK_P and SYSCLK_N and each signal is connected to U1 (pins H9 and G9, respectively) on the XC7Z045 SoC.
•
Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)
•
Frequency tolerance: 50 ppm
•
LVDS Differential Output
The system clock circuit is shown in Figure 1-12.
For more details, see the SiTime SiT9102 data sheet [Ref 21].
Programmable User Clock
[Figure 1-3, callout 8]
The ZC706 evaluation board has a programmable low-jitter 3.3V LVDS differential oscillator (U37) connected to the MRCC inputs of bank 10. This USRCLK_P and USRCLK_N clock signal pair is connected to XC7Z045 SoC U1 pins AF14 and AG14, respectively. On power-up the user clock defaults to an output frequency of 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I C interface. Power cycling the ZC706 evaluation board reverts the user clock to the default frequency of 156.250 MHz.
•
Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz)
•
Frequency tolerance: 50 ppm
•
LVDS Differential Output
X-Ref Target - Figure 1-12
Figure 1-12: System Clock Source
UG954_c1_11_041113
GND
VCC2V5
SIT9102
200 MHz
Oscillator
OE
NC
GND
VCC
OUT_B
OUT
1
2
3
6
5
4
U64
R322
100Ω
1/20W 5%
SYSCLK_P
SYSCLK_N
C89
0.1 μF 10V
X5R
1
2
2
1
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UG954 (v1.8) August 6, 2019
Feature Descriptions
The user clock circuit is shown in Figure 1-13.
See the Silicon Labs Si570 data sheet [Ref 22].
User SMA Clock Source
The ZC706 board provides a pair of SMAs for differential user clock input into PL Bank 9 (see Figure 1-14). The P-side SMA J67 signal USER_SMA_CLOCK_P is connected to U1 pin AD18, with the N-side SMA J68 signal USER_SMA_CLOCK_N connected to U1 pin AD19. Bank 9 Vcco is VADJ_FPGA, a variable voltage (1.8V, 2.5V, 3.3V) depending on the ZC706 FMC interface banks voltage. The USER_SMA_CLOCK input voltage swing should not exceed the board VADJ_FPGA voltage setting.
X-Ref Target - Figure 1-13
Figure 1-13: User Clock Source
X-Ref Target - Figure 1-14
Figure 1-14: User SMA Clock
UG954_c1_12_041113
GND
VCC3V3
1
2
3
8
7
6
U37
R37
4.7KΩ
1/10W
5%
C348
0.01 μF 25V
X7R
4
5
GND
VCC3V3
10 MHz-810 MHz
50PPM
Si570
Programmable
Oscillator NC
OE
GND
SCL
SDA
VDD
OUT_B-
OUT+
R323
100Ω
1/20W 5%
USRCLK SFP SDA USRCLK SFP SCL
USRCLK N
USRCLK P
1
2
1
2
1
2
UG954_c1_13_041113
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Processing System Clock Source
The Processing System (PS) clock source is a 1.8V LVCMOS single-ended fixed 33.33333 MHz oscillator at U24. It is wired to PS bank 500, pin A22 (PS_CLK), on the XC7Z045 SoC.
•
Oscillator: SiTime SiT8103AC-23-18E-33.33333 (33.3 MHz)
•
Frequency tolerance: 50 ppm
•
Single-ended output
The system clock circuit is shown in Figure 1-15.
For more details, see the SiTime SiT8103 data sheet [Ref 21].
GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N)
[Figure 1-3, callout 10]
The ZC706 board includes a pair of SMA connectors for a GTX clock wired to GTX Quad bank 111. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to SoC U1 pins W8 and W7 respectively.
•
External user-provided GTX reference clock on SMA input connectors
•
Differential Input
X-Ref Target - Figure 1-15
Figure 1-15: Processing System Clock Source
UG954_c1_14_041113
GND
VCCP1V8
SiT8103
Oscillator
33.33333 MHz
50 PPM
OE
GND
VCC
1
2
4
U24
R38
4.7KΩ
1/10W
5%
C349
0.01 μF 25V
X7R
3
GND
VCCP1V8
OUT
R173
24.9Ω
1/10W 1%
PS CLK
1
2
1
2
1
2
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Figure 1-16 shows this AC-coupled clock circuit.
Jitter Attenuated Clock
[Figure 1-3, callout 11]
The ZC706 board includes a Silicon Labs Si5324 jitter attenuator U60 on the back side of the board. SoC user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 9 (REC_CLOCK_C_P, SoC U1 pin AD20 and REC_CLOCK_C_N, SoC U1 pin AE20) for jitter attenuation. The jitter attenuated clock (Si5324_OUT_C_P, Si5324_OUT_C_N) is then routed as a reference clock to GTX Quad 110 inputs MGTREFCLK1P (SoC U1 pin AC8) and MGTREFCLK1N (SoC U1 pin AC7).
The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTX transceiver. The jitter attenuated clock circuit is shown in Figure 1-17.
X-Ref Target - Figure 1-16
Figure 1-16: GTX SMA Clock Source
UG954_c1_15_041113
SMA_MGT_REFCLK_P
SMA_MGT_REFCLK_C_P
SMA
Connector
J36
GND
C145
0.01 μF 25V
X7R
SMA_MGT_REFCLK_N
SMA_MGT_REFCLK_C_N
SMA
Connector
J31
GND
C144
0.01 μF 25V
X7R
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UG954 (v1.8) August 6, 2019
Feature Descriptions
See the Silicon Labs Si5324 data sheet [Ref 22].
GTX Transceivers
[Figure 1-3, callout 12]
The ZC706 board provides access to 16 GTX transceivers:
•
Four of the GTX transceivers are wired to the PCI Express x4 endpoint edge connector (P4) fingers
•
Eight of the GTX transceivers are wired to the FMC HPC connector (J37)
•
One GTX transceiver is wired to the FMC LPC connector (J5)
•
One GTX transceiver is wired to SMA connectors (RX: J32, J33 TX: J35, J34)
•
One GTX transceiver is wired to the SFP/SFP+ Module connector (P2)
X-Ref Target - Figure 1-17
Figure 1-17: Jitter Attenuated Clock
UG954_c1_16_041113
R89
4.7 KΩ 5%
SI5324_VCC
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
VDD3
GND
XB
XA
NC5
32
6
30
29
28
U60
CKOUT1_N
7
33
CKOUT1_P
C137
0.1 μF 25V
X5R
C136
0.1 μF 25V
X5R
SI5324_XTAL_XA
GND2
GND1
XB
XA
X4
114.285 MHz
20 ppm
SI5324_OUT_C_N
SI5324_OUT_C_P
SI5324_OUT_N
SI5324_OUT_P
SI5324_XTAL_XB
GND
NC4
2
1
3
4
C138
0.1 μF 25V
X5R
C141
0.1 μF 25V
X5R
REC_CLOCK_P
REC_CLOCK_N
REC_CLOCK_C_P
REC_CLOCK_C_N
16
17
R251
100Ω
CKIN1_P
CKIN1_N
NC
NC
12
13
CKIN2_P
CKIN2_N
10
5
VDD2
VDD1
14
NC3
9
NC2
2
NC1
NC
NC
NC
NC
NC
35
34
NC
NC
CKOUT2_P
CKOUT2_N
SI5324_INT_ALM
3
NC 4
NC 11
NC 15 NC 18
19
20
SI5324_RST
1
21
31
GND2
9
GND1
31
A2_SS
31
A1
24
A0
22
RTC SI5324_SCL
SCL
23
RTC SI5324_SDA
SDA_SDO
27
NC
SDI
36
CMODE
GND
GND4
GND3
LOL
RATE1
RATE0
C2B
INT_C1B
CS_CA
RST_B
37
GNDPAD
0.1W
1%
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UG954 (v1.8) August 6, 2019
Feature Descriptions
•
One GTX transceiver is unused and is wired in a capacitively coupled TX-to-RX loopback configuration
The GTX transceivers in Zynq-7000 series SoCs are grouped into four channels described as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below the GTX Quad of interest. There are four GTX Quads on the ZC706 board with connectivity as shown here:
•
Quad 109:
°
MGTREFCLK0 - FMC_HPC_GBTCLK0_M2C clock
°
MGTREFCLK1 - not connected
°
Contains 4 GTX transceivers allocated to FMC_HPC_DP[3:0]_C2M_P/N
•
Quad 110:
°
MGTREFCLK0 - FMC_HPC_GBTCLK1_M2C clock
°
MGTREFCLK1 - SI5324_OUT_C_P/N jitter attenuator clock
°
Contains 4 GTX transceivers allocated to FMC_HPC_DP[7:4]_C2M_P/N
•
Quad 111:
°
MGTREFCLK0 - FMC_LPC_GBTCLK0_M2C_C_P/N
°
MGTREFCLK1 - SMA_MGT_REFCLK_P/N SMA GTX clock input
°
Contains 1 GTX transceiver allocated to FMC_LPC_DP0_C2M_P/N
°
Contains 1 GTX transceiver allocated to SMA_MGT_TX_P/N and RX_P/N SMA connectors
°
Contains 1 GTX transceiver allocated to SFP_TX and _RX_P/N SFP/SFP+ connector
°
Contains 1 GTX transceiver which is unused and is wired in TX-to-RX loopback configuration
•
Quad 112:
°
MGTREFCLK0 - PCIE_CLK_Q0_P/N PCIe edge connector clock
°
MGTREFCLK1 - not connected
°
Contains 4 GTX transceivers allocated to PCIe lanes 0-3
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-15 lists the GTX Banks 109 and 110 interface connections between the SoC U1 and FMC HPC connector J37.
Table 1-14: SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37
Transceiver
Bank
SoC U1
Pin
Number
SoC U1 Pin Name
Schematic Net Name
Connected
Pin
Connected
Device
GTX_BANK_109
AK10
MGTPTXP0_109
FMC_HPC_DP0_C2M_P
C2
FMC HPC
J37
AK9
MGTPTXN0_109
FMC_HPC_DP0_C2M_N
C3
AH10
MGTPRXP0_109
FMC_HPC_DP0_M2C_P
C6
AH9
MGTPRXN0_109
FMC_HPC_DP0_M2C_N
C7
AK6
MGTPTXP1_109
FMC_HPC_DP1_C2M_P
A22
AK5
MGTPTXN1_109
FMC_HPC_DP1_C2M_N
A23
AJ8
MGTPRXP1_109
FMC_HPC_DP1_M2C_P
A2
AJ7
MGTPRXN1_109
FMC_HPC_DP1_M2C_N
A3
AJ4
MGTPTXP2_109
FMC_HPC_DP2_C2M_P
A26
AJ3
MGTPTXN2_109
FMC_HPC_DP2_C2M_N
A27
AG8
MGTPRXP2_109
FMC_HPC_DP2_M2C_P
A6
AG7
MGTPRXN2_109
FMC_HPC_DP2_M2C_N
A7
AK2
MGTPTXP3_109
FMC_HPC_DP3_C2M_P
A30
AK1
MGTPTXN3_109
FMC_HPC_DP3_C2M_N
A31
AE8
MGTPRXP3_109
FMC_HPC_DP3_M2C_P
A10
AE7
MGTPRXN3_109
FMC_HPC_DP3_M2C_N
A11
AD10
MGTREFCLK0P_109
FMC_HPC_GBTCLK0_M2C_C_P
D4
AD9
MGTREFCLK0N_109
FMC_HPC_GBTCLK0_M2C_C_N D5
AF10
MGTREFCLK1P_109
NC
NA
NA
AF9
MGTREFCLK1N_109
NC
NA
NA
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UG954 (v1.8) August 6, 2019
Feature Descriptions
GTX_BANK_110
AH2
MGTPTXP0_110
FMC_HPC_DP4_C2M_P
A34
FMC HPC
J37
AH1
MGTPTXN0_110
FMC_HPC_DP4_C2M_N
A35
AH6
MGTPRXP0_110
FMC_HPC_DP4_M2C_P
A14
AH5
MGTPRXN0_110
FMC_HPC_DP4_M2C_N
A15
AF2
MGTPTXP1_110
FMC_HPC_DP5_C2M_P
A38
AF1
MGTPTXN1_110
FMC_HPC_DP5_C2M_N
A39
AG4
MGTPRXP1_110
FMC_HPC_DP5_M2C_P
A18
AG3
MGTPRXN1_110
FMC_HPC_DP5_M2C_N
A19
AE4
MGTPTXP2_110
FMC_HPC_DP6_C2M_P
B36
AE3
MGTPTXN2_110
FMC_HPC_DP6_C2M_N
B37
AF6
MGTPRXP2_110
FMC_HPC_DP6_M2C_P
B16
AF5
MGTPRXN2_110
FMC_HPC_DP6_M2C_N
B17
AD2
MGTPTXP3_110
FMC_HPC_DP7_C2M_P
B32
AD1
MGTPTXN3_110
FMC_HPC_DP7_C2M_N
B33
AD6
MGTPRXP3_110
FMC_HPC_DP7_M2C_P
B12
AD5
MGTPRXN3_110
FMC_HPC_DP7_M2C_N
B13
AA8
MGTREFCLK0P_110
FMC_HPC_GBTCLK1_M2C_P
B20
AA7
MGTREFCLK0N_110
FMC_HPC_GBTCLK1_M2C_N
B21
AC8
MGTREFCLK1P_110
SI5324_OUT_C_P
28
SI5324C
U60
AC7
MGTREFCLK1N_110
SI5324_OUT_C_N
29
Notes:
1.
SoC U1 GTX input clock nets are capacitively coupled to the FMC HPC J37 pins.
2.
SoC U1 GTX input clock nets are capacitively coupled to the SI5324C Recovery Clock U60 output pins.
Table 1-14: SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37 (Cont’d)
Transceiver
Bank
SoC U1
Pin
Number
SoC U1 Pin Name
Schematic Net Name
Connected
Pin
Connected
Device
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-15 lists the GTX Bank interface connections between the SoC U1 and FMC LPC connector J5.
For additional information on Zynq-7000 GTX transceivers, see 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
Table 1-15: SoC GTX Bank 111 Interface Connections to FMC LPC J5
Transceiver
Bank
SoC U1 Pin
Number
SoC U1 Pin Name
Schematic Net Name
Connected
Pin
Connected
Device
GTX_BANK_11
1
AB2
MGTPTXP0_111
FMC_LPC_DP0_C2M_P
C2
FMC LPC
J5
AB1
MGTPTXN0_111
FMC_LPC_DP0_C2M_N
C3
AC4
MGTPRXP0_111
FMC_LPC_DP0_M2C_P
C6
AC3
MGTPRXN0_111
FMC_LPC_DP0_M2C_N
C7
Y2
MGTPTXP1_111
SMA_MGT_TX_P
J35.1
GTX TX/RX
SMA
Y1
MGTPTXN1_111
SMA_MGT_TX_N
J34.1
AB6
MGTPRXP1_111
SMA_MGT_RX_P
J32.1
AB5
MGTPRXN1_111
SMA_MGT_RX_N
J33.1
W4
MGTPTXP2_111
SFP_TX_P
18
SFP+
Conn. P2
W3
MGTPTXN2_111
SFP_TX_N
19
Y6
MGTPRXP2_111
SFP_RX_P
13
Y5
MGTPRXN2_111
SFP_RX_N
12
V2
MGTPTXP3_111
(capacitively coupled to AA4)
U1.AA4
SoC U1
GTX
Loopback
V1
MGTPTXN3_111
(Cooperatively coupled to AA3)
U1.AA3
AA4
MGTPRXP3_111
See Pin V2 loopback
U1.V2
AA3
MGTPRXN3_111
See Pin V1 loopback
U1.V1
U8
MGTREFCLK0P_111
FMC_LPC_GBTCLK0_M2C_C_P
D4
FMC LPC
J5
U7
MGTREFCLK0N_111
FMC_LPC_GBTCLK0_M2C_C_N D5
W8
MGTREFCLK1P_111
SMA_MGT_REFCLK_P
J36.1
GTX
REFCLK
SMA
W7
MGTREFCLK1N_111
SMA_MGT_REFCLK_N
J31.1
Notes:
1.
SoC U1 GTX input clock nets are capacitively coupled to the FMC LPC J5 pins.
2.
SoC U1 GTX input nets are capacitively coupled to the RX and MGT_REFCLK SMA pins.
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UG954 (v1.8) August 6, 2019
Feature Descriptions
PCI Express Endpoint Connectivity
[Figure 1-3, callout 13]
The 4-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair.
The XC7Z045-2FFG900C SoC (-2 speed grade) included with the ZC706 board supports up to Gen2 x4.
The PCIe clock is input from the edge connector. It is AC coupled to the SoC through the MGTREFCLK0 pins of Quad 112. PCIE_CLK_Q0_P is connected to SoC U1 pin N8, and the _N net is connected to pin N7. The PCI Express clock circuit is shown in Figure 1-18.
PCIe lane width/size is selected by jumper J19 (Figure 1-18). The default lane size selection is 4-lane (J19 pins 3 and 4 jumpered).
X-Ref Target - Figure 1-18
Figure 1-18: PCI Express Clock
UG954_c1_17_041113
PCI Express
Eight-Lane
Edge connector
GND
GND
A15
A13
A14
P4
REFCLK+
A12
GND
C352
0.01μF 25V
X7R
C353
0.01μF 25V
X7R
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
PCIE_CLK_Q0_C_P
PCIE_CLK_Q0_C_N
OE
REFCLK-
X-Ref Target - Figure 1-19
Figure 1-19: PCI Express Lane Size Select Jumper J19
UG954_c1_18_041113
PCIE_PRSNT_B
PCIE_PRSNT_X1
PCIE_PRSNT_X4
J19 1
3
2
4
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-18 lists the GTX Bank 112 interface connections between the SoC U1 and PCIe 4-lane connector P4.
For additional information about Zynq-7000 PCIe functionality, see 7 Series FPGAs
Integrated Block for PCI Express Product Guide for Vivado Design Suite (PG054). Additional information about the PCI Express standard is available [Ref 23].
Table 1-16: SoC GTX Bank 112 Interface Connections to PCIe 4-Lane Connector P4
Transceiver
Bank
SoC U1 Pin Number
SoC U1 Pin Name
Schematic Net Name
PCIe 4-Lane Conn. P4
Pin Number
GTX_BANK_112
T2
MGTPTXP0_112
PCIE_TX3_P
A29 (1)
T1
MGTPTXN0_112
PCIE_TX3_N
A30 (1)
V6
MGTPRXP0_112
PCIE_RX3_P
B27
V5
MGTPRXN0_112
PCIE_RX3_N
B28
R4
MGTPTXP1_112
PCIE_TX2_P
A25 (1)
R3
MGTPTXN1_112
PCIE_TX2_N
A26 (1)
U4
MGTPRXP1_112
PCIE_RX2_P
B23
U3
MGTPRXN1_112
PCIE_RX2_N
B24
P2
MGTPTXP2_112
PCIE_TX1_P
A21 (1)
P1
MGTPTXN2_112
PCIE_TX1_N
A22 (1)
T6
MGTPRXP2_112
PCIE_RX1_P
B19
T5
MGTPRXN2_112
PCIE_RX1_N
B20
N4
MGTPTXP3_112
PCIE_TX0_P
A16 (1)
N3
MGTPTXN3_112
PCIE_TX0_N
A17 (1)
P6
MGTPRXP3_112
PCIE_RX0_P
B14
P5
MGTPRXN3_112
PCIE_RX0_N
B15
N8
MGTREFCLK0P_112
PCIE_CLK_QO_P
A13 (1)
N7
MGTREFCLK0N_112
PCIE_CLK_QO_N
A14 (1)
R8
MGTREFCLK1P_112
NC
NA
R7
MGTREFCLK1N_112
NC
NA
Notes:
1.
PCIE_TXn_P/N and PCIE_CLK_Q0_P/N are capacitively coupled to the PCIe edge connector P4.
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UG954 (v1.8) August 6, 2019
Feature Descriptions
SFP/SFP+ Module Connector
[Figure 1-3, callout 14]
The ZC706 board contains a small form-factor pluggable (SFP/SFP+) connector and cage assembly P2 that accepts SFP or SFP+ modules. Figure 1-20 shows the SFP/SFP+ module connector circuitry.
Table 1-17 lists the SFP+ module RX and TX connections to the SoC.
X-Ref Target - Figure 1-20
Figure 1-20: SFP+ Module Connector
UG954_c1_19_041113
GND12
GND1
GND2 GND3
GND4 GND5
GND6
GND7 GND8
GND9
GND10
TD_N
TD_P
VCCT
VCCR
RD_P
RD_N
LOS
VEET_3
VEET_2
VEER_3
VEER_1
VEER_2
VEET_1
RS0
RS1
MOD_ABS
SCL
SDA
TX_DISABLE
TX_FAULT
GND11
2-3: LOW BW TX
2-3: LOW BW RX
1-2: FULL BW RX
SFP Enable
1-2: FULL BW TX
SFP_RS1
SFP_VCCT
32
21
22
23
24
25
26
27
28
29
30
19
18
16
15
13
12
8
20
17
14
10
11
1
7
9
6
5
4
3
2
31
P2
SFP+ Module
Connector
74441-0010
SFP_LOS
SFP_TX_FAULT
SFP_IIC_SDA
SFP_IIC_SCL
SFP_RX_P
SFP_RX_N
SFP_TX_P
SFP_TX_DISABLE_TRANS
SFP_RS0
3
2
1
J38
J39
1
2
J17
HDR_1X2
SFP_MOD_DETECT
1
J21
SFP_TX_N
SFP_VCCR
R87
4.7KΩ
L7
4.7μH
3.0 A
VCC3V3
C135
0.1μF
GND
VCC3V3
L6
4.7μH
3.0 A
C199
22μF
C134
0.1μF
C198
22μF
GND
1
Q12
NDS331N
460 mW SFP_TX_DISABLE
3
2
R84
4.7KΩ
VCC3V3
GND
R83
4.7KΩ
R85
4.7KΩ
R86
4.7KΩ
1
J22
1
HDR_1X1
J20
HDR_1X3
R88
4.7KΩ
VCC3V3
VCC3V3
GND
GND
1
2
3
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Feature Descriptions
Table 1-18 lists the SFP+ module control and status connections to the SoC.
For additional information about the enhanced Small Form Factor Pluggable (SFP+) module, see the SFF-8431 specification [Ref 24].
10/100/1000 Mb/s Tri-Speed Ethernet PHY (PS)
[Figure 1-3, callout 15]
The ZC706 evaluation board uses the Marvell Alaska PHY device (88E1116R) at U51 for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P3) with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY address 0b00111 using the settings shown in Table 1-19. These settings can be overwritten via software commands passed over the MDIO interface.
Table 1-17: SoC U1 to SFP+ Module Connections
SoC (U1) Pin
Schematic Net name
SFP+ Module (P2)
Pin
Name
Y5
SFP_RX_N
12
RD_N
Y6
SFP_RX_P
13
RD_P
W4
SFP_TX_P
18
TD_P
W3
SFP_TX_N
19
TD_N
AA18
SFP_TX_DISABLE_TRANS
3
TX_DISABLE
Table 1-18: SFP+ Module Control and Status Connections
SFP Control/ Status
Signal
Board Connection
SFP_TX_FAULT
Test Point J23
High = Fault
Low = Normal operation
SFP_TX_DISABLE
Jumper 17
Off = SFP Disabled
On = SFP enabled
SFP_MOD_DETECT
Test Point J24
High = Module not present
Low = Module present
SFP_RS0
Jumper 56
Jumper pins 1-2 = Full RX bandwidth
Jumper pins 2-3 = Reduced RX bandwidth
SFP_RS1
Jumper 55
Jumper pins 1-2 = Full TX bandwidth
Jumper pins 2-3 = Reduced TX bandwidth
SFP_LOS
Test Point J25
High = Loss of receiver signal
Low = Normal operation
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Feature Descriptions
The Ethernet connections from the XC7Z045 SoC at U1 to the 88E1116R PHY device at U51 are listed in Table 1-20.
Ethernet PHY Clock Source
A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 881116R PHY at U51.
Figure 1-21 shows the clock source.
Table 1-19: Board Connections for PHY Configuration Pins
U51 Pin
Setting
Configuration
CONFIG (64)
VCCP1V8
PHYAD[1]=1
PHYAD[0]=1
CONFIG1 (1)
PHY_LED0
PHYAD[3]=0
PHYAD[2]=1
CONFIG2 (2)
GND
ENA_XC=0
PHYAD[4]=0
PHY_LED0
ENA_XC=0
PHYAD[4]=1
VCCP1V8
ENA_XC=1
PHYAD[4]=1
CONFIG3 (3)
GND
RGMII_TX=0
RGMII_RX=0
PHY_LED0
RGMII_TX=0
RGMII_RX=1
PHY_LED1
RGMII_TX=1
RGMII_RX=0
VCCP1V8
RGMII_TX=1
RGMII_RX=1
Table 1-20: Ethernet Connections, XC7Z045 SoC to the PHY Device
XC7Z045 (U1) Pin
Schematic
Net Name
M88E1116R PHY U51
Pin Name
Bank
Pin
Number
Pin
Name
PS_MIO53
501
C18
PHY_MDIO
45
MDIO
PS_MIO52
501
D19
PHY_MDC
48
MDC
PS_MIO16
501
L19
PHY_TX_CLK
60
TX_CLK
PS_MIO21
501
J19
PHY_TX_CTRL
63
TX_CTRL
PS_MIO20
501
M20
PHY_TXD3
62
TXD3
PS_MIO19
501
J20
PHY_TXD2
61
TXD2
PS_MIO18
501
K20
PHY_TXD1
59
TXD1
PS_MIO17
501
K21
PHY_TXD0
58
TXD0
PS_MIO22
501
L20
PHY_RX_CLK
53
RX_CLK
PS_MIO27
501
G20
PHY_RX_CTRL
49
RX_CTRL
PS_MIO26
501
M17
PHY_RXD3
55
RXD3
PS_MIO25
501
G19
PHY_RXD2
54
RXD2
PS_MIO24
501
M19
PHY_RXD1
51
RXD1
PS_MIO23
501
J21
PHY_RXD0
50
RXD0
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Feature Descriptions
The data sheet can be obtained under NDA with Marvell. Contact information can be found at their website [Ref 25].
For additional information on the Zynq-7000 SoC device gigabit Ethernet controller, see
Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
USB-to-UART Bridge
[Figure 1-3, callout 17]
The ZC706 evaluation board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U52) which allows a connection to a host computer with a USB port. The USB cable is supplied in the ZC706 evaluation kit (Standard-A end to host computer, Type Mini-B end to ZC706 evaluation board connector J21). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the ZC706 evaluation board.
The CP2013GM TX and RX pins are wired to the UART_1 IP block within the XC7Z045 SoC PS I/O Peripherals set. The XC7Z045 SoC supports the USB-to-UART bridge using two signal pins: Transmit (TX) and Receive (RX).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm or HyperTerm) that runs on the host computer. The VCP device drivers must be installed on the host PC prior to establishing communications with the ZC706 evaluation board.
The USB Connector pin assignments and signal definitions between J21 and U52 are listed in Table 1-21.
X-Ref Target - Figure 1-21
Figure 1-21: Ethernet PHY Clock Source
UG954_c1_20_041113
GND
R355
DNP
C495
18 pF 50V
NPO
C494
18 pF 50V
NPO
PHY XTAL OUT
X1 25.00 MHz
50 PPM
PHY XTAL IN
3
4
1
2
1
2
1
2
1
2
NC
NC
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-22 lists the USB connections between the XC7Z045 SoC PS Bank 501 and the CP2103 UART bridge.
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers [Ref 22].
For additional information on the Zynq-7000 SoC device UART controller, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
HDMI Video Output
[Figure 1-3, callout 18]
The ZC706 evaluation board provides a high-definition multimedia interface (HDMI®) video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U53. The HDMI transmitter U53 is connected to the XC7Z045 SoC PL-side banks 12 and 13 and its output is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports 1080P 60Hz, YCbCr 4:4:4 encoding via 24-bit input data mapping.
The ZC706 evaluation board supports the following HDMI device interfaces:
•
24 data lines
•
Independent VSYNC, HSYNC
•
Single-ended input CLK
•
Interrupt Out pin to XC7Z045 SoC
Table 1-21: USB Connector J21 Pin Assignments and Signal Definitions
USB Connector (J21)
Net Name
Description
CP2103GM (U52)
Pin
Name
Pin
Name
1
VBUS
USB_UART_VBUS
+5V VBUS Powered
7
REGIN
8
VBUS
2
D_N
USB_UART_D_N
Bidirectional differential serial data (N-side)
4
D –
3
D_P
USB_UART_D_P
Bidirectional differential serial data (P-side)
3
D +
5
GND
USB_UART_GND
Signal ground
2
GND1
29
CNR_GND
Table 1-22: XC7Z045 SoC to CP2103 Connections
XC7045 SoC (U1)
Schematic Net
Name
CP2103GM Device (U52)
Pin Name Bank PIN Function Direction IOSTANDARD
PIN Function Direction
PS_MIO48
501
C19
TX
Output
LVCMOS18
USB_UART_RX
24
RXD
Input
PS_MIO49
501
D18
RX
Input
LVCMOS18
USB_UART_TX
25
TXD
Output
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UG954 (v1.8) August 6, 2019
Feature Descriptions
•
I C
•
SPDIF
Figure 1-22 shows the HDMI codec circuit.
X-Ref Target - Figure 1-22
Figure 1-22: HDMI Codec Circuit
UG954_c1_21_041113
GND
GND
VCC3V3
GND
GND
OE
GND
OUT
VCC
D31 D32
D33
D34
D35
D12
D13 D14
D15
D29
D30
D1
D4
D5
D6
D28
D27
D26
D25
D24
D23
D22
D21
D20
D0
D19
D3
D2
D11
D10
D9
D8
D7
D16
GND10
DE
CLK
D18
D17
SPDIF
VSYNC
HSYNC
SDA
SCL
CEC_CLK
SPDIF_OUT
INT
PD
PVDD1
PVDD2
PVDD3
AVDD2
AVDD3
AVDD1
GND1
GND2
GND6
GND3
GND4
GND5
GND7
GND8
GND9
GND11
DVDD_3V
BGVDD
DVDD1
DVDD2
DVDD3
DVDD4
DVDD5
HPD
To HDMI
Connector
HDMI_SPDIF_OUT
61
60
59
58
57
84
83
82
81
63
62
95
92
91
90
64
65
66
67
68
69
70
71
72
96
73
93
94
85
86
87
88
89
80
44
97
79
74
78
10
2
98
56
55
50
46
45
38
21
24
25
34
41
29
99
100
23
18
20
22
27
31
37
75
47
26
76
77
49
19
1
30
U53 ADV7511
HDMI_D10
VADJ
HDMI_HEAC_C_N
HDMI_AVDD
HDMI_PLVDD
HDMI_PLVDD
2
1
X5R
25V
0.1μF
C88
HDMI_CLK
HDMI_HSYNC
HDMI_VSYNC
HDMI_INT
1
1%
1/10W
2.43KΩ
R165
R164
2.43 KΩ
1/10W
1%
IIC_SCL_HDMI
1
2
3
4
U50
12.00000 MHZ SIT8102
50 PPM
VCC2V5
IIC_SDA_HDMI
HDMI_DVDD
HDMI_DE
R163
2.43 KΩ
1/10W
1%
HDMI_SPDIF
HDMI_AVDD
HDMI_DVDD_3V
HDMI_D4
HDMI_D5
HDMI_D7
HDMI_D8
HDMI_D9
HDMI_D11
HDMI_D6
HEAC_P
HEAC_N
TX2_P
TX2_N
TX1_P
TX1_N
TX0_P
TX0_N
TXC_P
TXC_N
DDCSDA
DDCSCL
CEC
52
51
43
42
40
39
36
35
33
32
54
53
48
HDMI_CEC
HDMI_DDCSDA
HDMI_D0_P
HDMI_DDCSCL
HDMI_HEAC_N
HDMI_HEAC_P
HDMI_CLK_N
HDMI_CLK_P
HDMI_D2_N
HDMI_D2_P
HDMI_D1_N
HDMI_D1_P
HDMI_D0_N
To HDMI
Connector
DSD0
DSD1
DSD2
DSD3
DSD4
DSD5
DSD_CLK
I2S0
I2S2
I2S1
LRCLK
SCLK
I2S3
R_EXT
MCLK
2
1
2
1
2
1
2
3
4
5
6
7
8
9
12
14
13
17
16
15
28
11
R158
887Ω
1/10W 1%
R172
24.9Ω
1/10W 1%
HDMI_D22
HDMI_D16
HDMI_D17
HDMI_D19
HDMI_D20
HDMI_D21
HDMI_D23
HDMI_D18
HDMI_D34
HDMI_D28
HDMI_D28
HDMI_D31
HDMI_D32
HDMI_D33
HDMI_D35
HDMI_D30
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Feature Descriptions
Table 1-23 lists the connections between the codec and the XC7Z045 SoC.
Table 1-23: XC7Z045 SoC U1 to HDMI Codec Connections (ADV7511)
XC7Z045 (U1)
Pin
Net Name
I/O Standard
ADV7511 (U53)
Pin Number
Pin Name
U24
HDMI_R_D4
LVCMOS25
92
D4
T22
HDMI_R_D5
LVCMOS25
91
D5
R23
HDMI_R_D6
LVCMOS25
90
D6
AA25
HDMI_R_D7
LVCMOS25
89
D7
AE28
HDMI_R_D8
LVCMOS25
88
D8
T23
HDMI_R_D9
LVCMOS25
87
D9
AB25
HDMI_R_D10
LVCMOS25
86
D10
T27
HDMI_R_D11
LVCMOS25
85
D11
AD26
HDMI_R_D16
LVCMOS25
80
D16
AB26
HDMI_R_D17
LVCMOS25
78
D17
AA28
HDMI_R_D18
LVCMOS25
74
D18
AC26
HDMI_R_D19
LVCMOS25
73
D19
AE30
HDMI_R_D20
LVCMOS25
72
D20
Y25
HDMI_R_D21
LVCMOS25
71
D21
AA29
HDMI_R_D22
LVCMOS25
70
D22
AD30
HDMI_R_D23
LVCMOS25
69
D23
Y28
HDMI_R_D28
LVCMOS25
64
D28
AF28
HDMI_R_D29
LVCMOS25
63
D29
V22
HDMI_R_D30
LVCMOS25
62
D30
AA27
HDMI_R_D31
LVCMOS25
61
D31
U22
HDMI_R_D32
LVCMOS25
60
D32
N28
HDMI_R_D33
LVCMOS25
59
D33
V21
HDMI_R_D34
LVCMOS25
58
D34
AC22
HDMI_R_D35
LVCMOS25
57
D35
V24
HDMI_R_DE
LVCMOS25
97
DE
R22
HDMI_R_HSYNC
LVCMOS25
98
HSYNC
U21
HDMI_R_VSYNC
LVCMOS25
2
VSYNC
P28
HDMI_R_CLK
LVCMOS25
79
CLK
AC23
HDMI_INT
LVCMOS25
45
INT
AC21
HDMI_R_SPDIF
LVCMOS25
10
SPDIF
AB22
HDMI_SPDIF_OUT_LS
LVCMOS25
46
SPDIF_OUT
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UG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-24 lists the connections between the codec and the HDMI receptacle P1.
Information about the ADV7511KSTZ-P is available on the Analog Devices website [Ref 26].
For additional information about HDMI IP options, see the LogiCORE IP DisplayPort Product Guide for Vivado Design Suite (PG064).
I2C Bus
[Figure 1-3, callout 20]
The ZC706 evaluation board implements two I C ports on the XC7Z045 SoC. The PL-side I C port (IIC_SDA and _SCL_MAIN) is routed to level shifter U87. The PS-side I C port (PS_SDA and _SCL_MAIN) is routed to level shifter U88. The "output" side of the two level shifters are wired to the common I C bus IIC_SDA and _SCL_MAIN which is connected to TI Semiconductor PCA9548 1-to-8 channel I C bus switch (U65). The bus switch can operated at speeds up to 400 kHz.
IMPORTANT: The PCA9548 U65 RESET_B pin 24 is connected to FPGA U1 bank 501 pin F20 via level-shifter U25. FPGA pin F20 net IIC_MUX_RESET_B_LS must be driven High to enable I2C bus transactions with the devices connected to U65.
Table 1-24: ADV7511 to HDMI Receptacle Connections
ADV7511 (U53)
Net Name
HDMI Receptacle
P1 Pin
36
HDMI_D0_P
7
35
HDMI_D0_N
9
40
HDMI_D1_P
4
39
HDMI_D1_N
6
43
HDMI_D2_P
1
42
HDMI_D2_N
3
33
HDMI_CLK_P
10
32
HDMI_CLK_N
12
54
HDMI_DDCSDA
16
53
HDMI_DDCSCL
15
52
HDMI_HEAC_P
14
51
HDMI_HEAC_N
19
48
HDMI_CEC
13
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Feature Descriptions
The ZC706 evaluation board I C bus topology is shown in Figure 1-23.
User applications that communicate with devices on one of the downstream I C buses must first set up a path to the desired bus through the U65 bus switch at I C address 0x74 (0b01110100). Table 1-25 lists the address for each bus.
Information about the PCA9548 is available on the TI Semiconductor website at [Ref 27].
For additional information on the Zynq-7000 SoC device I C controller, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
X-Ref Target - Figure 1-23
Figure 1-23: I C Bus Topology
CH7 - PMBUS_DATA/CLK
PCA9548
12C 1-to-8
Bus Switch
U65
CH6 - FMC_LPC_IIC_SDA/SCL
CH5 - FMC_HPC_IIC_SDA/SCL
CH4 - IIC_RTC_SDA/SCL
CH3 - PORT_EXPANDER_SDA/SCL
CH2 - EEPROM_IIC_SDA/SCL
CH1 - IIC_SDA/SCL_HDMI
CH0 - USRCLK_SFP_SDA/SCL
XC7Z045 AP SoC
PS Bank 501
(1.8V)
U1
UG954_c1_22_04113
XC7Z045 AP SoC
PL Bank 10
(2.5V)
U1
PCA9517
I C
Level Shifter
U87
3.3 V
VADJ 2.5V
A
B
PCA9517
I C
Level Shifter
U88
3.3 V
VCCMIO_PS 1.8V
A
B
IIC_SDA/SCL_MAIN
PS_SDA/SCL_MAIN
IIC_SCL/SDA_MAIN
Table 1-25: I C Bus Addresses
Device
I C Switch Position
I C Address
Device
PCA9548 8-Channel bus switch
NA
0b1110100
PCA9548 U65
Si570 clock
0
0b1011101
Si570 U37
0b1010000
SFP+ Conn. P2
ADV7511 HDMI
1
0b0111001
ADV7511 U53
I2C EEPROM
2
0b1010100
M24C08 U9
I2C port expander and DDR3 SODIMM
3
0b0100001
Port Expander U16
0b1010000
0b0011000
DDR3 SODIMM J1
I2C real time clock and Si5324 clock
4
0b1010001
RTC8564JE U26
0b1101000
SI5324 U60
FMC HPC
5
0bxxxxx00
FMC HPC J37
FMC LPC
6
0bxxxxx00
FMC LPC J5
UCD90120A pmbus
7
0b1100101
UCD90120A U48
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Feature Descriptions
Real Time Clock (RTC)
The Epson RTC-8564JE (U26) is an I C bus interface real-time clock that has a built-in 32.768 KHz oscillator with these features:
•
Frequency output options: 32.768 KHz, 1,024 Hz, 32 Hz or 1 Hz
•
Calendar output functions: Year, month, day, weekday, hour, minute and second
•
Clock counter, alarm and fixed-cycle timer interrupt functions
•
Back-up battery B3 Panasonic ML621S/DN, 3.0V rechargeable cell
Programming information for the RTC-8564JE is available in the RTC-8564JE/NB Application Manual [Ref 30].
Figure 1-24 shows the real time clock circuit.
Real time clock connections to the XC7Z045 SoC and the PCA9548 8-Channel bus switch are listed in Table 1-26. Refer to Table 1-25 for the RTC I C address.
Information about the RTC-8564JE is available at the Epson Electronics America website [Ref 31].
X-Ref Target - Figure 1-24
Figure 1-24: Real Time Clock Circuit
Table 1-26: Real Time Clock Connections
RTC-8564JE (U16) Pin
Net Name
Connects To
6
IIC_RTC_SCL
U65.11 (PCA9548 SC4)
7
IIC_RTC_SDA
U65.10 (PCA9548 SD4)
10
IIC_RTC_IRQ_1_B U1.AA17 (XC7Z045 SoC PL BANK 10)
UG954_c1_23_041113
VCC3V3
VCC2V5
VADJ
GND
IIC_RTC_SCL
B3
Panasonic
ML621S/DN
3V
C350
0.01μF
25V
X7R
1
J60
YELLOW
IIC_RTC_IRQ_1_B
IIC_RTC_SDA
D5
BAT54T1G
30V 400 mW
RTC-8564JE
Real Time Clock
Module
7
6
10
U26
16
15
14 13
INT
SCL
SDA
GND
CLKOUT
CLKOE
VCC
D4
BAT54T1G
30V 400 mW
D6
BAT54T1G
30V 400 mW
GND
GND
R270
10.0 KΩ
0.1W
R501
4.7 KΩ
0.1WW
1
2
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Feature Descriptions
Status and User LEDs
Table 1-27 defines the status and user LEDs.
Table 1-27: Status LEDs
Reference
Designator
Net Name
LED Color
Description
DS1
POR
RED
Processor System Power-ON reset is active
DS2
FPGA_INIT_B
GRN/RED
Green: FPGA initialization was successful Red: FPGA initialization is in progress
DS3
DONE
GRN
FPGA bit file download is complete
DS8
GPIO_LED_LEFT
GRN
Geographically LEFT located user LED
DS9
GPIO_LED_CENTER
GRN
Geographically CENTER located user LED
DS10
GPIO_LED_RIGHT
GRN
Geographically RIGHT located user LED
DS11
VCCINT
GRN
VCCINT voltage on indicator
DS13
VCC1V5_PL
GRN
VCC1V5_PL voltage on indicator
DS15
VADJ_FPGA
GRN
VADJ_FPGA voltage on indicator
DS16
VCC3V3_FPGA
GRN
VCC3V3 voltage on indicator
DS20
PS_DDR_LINEAR_PG
GRN
VTTDDR_PS voltage on indicator
DS21
SODIMM_DDR_LINEAR_PG
GRN
VTTDDR_SODIMM voltage on indicator
DS22
VCC12_P
GRN
VCC12_P voltage on indicator
DS23
PWRCTL1_FMC_PG_C2M
GRN
FMC power good INDICATOR
DS24
CTRL1_PWRGOOD
GRN
Power Controller controlled voltage regulator outputs are all ≥ their minimum “good” threshold
DS25
U22_FLG
RED
USB 2.0 MOSFET power switch fault
DS26
LINEAR_POWER_GOOD
GRN
MGTAVCC, MGTAVTT, MGTVCCAUX voltage regulator outputs are all ≥ their minimum “good” threshold
DS27
VCCAUX
GRN
VCCAUX voltage on indicator
DS28
PHY_LED0
GRN
Ethernet PHY LED0
DS29
PHY_LED1
GRN
Ethernet PHY LED1
DS30
PHY_LED2
GRN
Ethernet PHY LED2
DS35
GPIO_LED_0
GRN
General Purpose user LED
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Feature Descriptions
Ethernet PHY User LEDs
[Figure 1-3, callout 21]
The three Ethernet PHY user LEDs shown in Figure 1-25 are located near the RJ45 Ethernet jack P3. The on/off state for each LED is software dependent and has no specific meaning at Ethernet PHY power on.
Refer to the Marvell 881116R Alaska Gigabit Ethernet transceiver data sheet for details concerning the use of the Ethernet PHY user LEDs. They are referred to in the data sheet as LED0, LED1, and LED2. See the data sheet and other product information for the Marvell 881116R Alaska Gigabit Ethernet Transceiver [Ref 25].
User I/O
[Figure 1-3, callout 22–24]
The ZC706 evaluation board provides the following user and general purpose I/O capabilities:
•
Four user LEDs (callout 22)
°
GPIO_LED_LEFT DS8, GPIO_LED_CENTER DS9, GPIO_LED_RIGHT DS10, GPIO_LED_0 DS35
•
Three user pushbuttons (callout 23)
°
GPIO_SW_LEFT SW7, GPIO_SW_CENTER SW9, GPIO_SW_RIGHT SW8
•
PL CPU reset pushbutton
°
PL_CPU_RESET SW13
•
4-position user DIP Switch (callout 24)
X-Ref Target - Figure 1-25
Figure 1-25: Ethernet PHY User LEDs
UG954_c1_24_041113
1
3
2
Q4
NDS331N
460 mW
DS30
VCC3V3
PHY LED 2
1
3
2
Q6
NDS331N
460 mW
DS28
VCC3V3
PHY LED 0
388
261Ω
0.1W
1
3
2
Q5
NDS331N
460 mW
DS29
VCC3V3
PHY LED1
387
261Ω
0.1W
GND
GND
GND
386
261Ω
0.1W
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Feature Descriptions
°
GPIO_DIP_SW[3:0] SW12
•
Two user GPIO male pin headers (callout 26)
•
2 x 6 0.1 in. pitch PMOD1 J57
•
2 x 6 0.1 in. pitch PMOD2 J58
User LEDs
[Figure 1-3, callout 22]
The ZC706 evaluation board supports four user LEDs connected to XC7Z045 SoC Banks 11, 33, and 35. Figure 1-26 shows the user LED circuits.
Table 1-28 lists the user LED connections to XC7Z045 SoC U1.
X-Ref Target - Figure 1-26
Figure 1-26: User LEDs
UG954_c1_25_041113
1
3
2
1
2
1
2
Q7
NDS331N
460 mW
DS8
VCC3V3
R390
261Ω
0.1W
1%
GND
1
3
2
Q8
NDS331N
460 mW
DS9
VCC3V3
R391
261Ω
0.1W
1%
GND
1
3
2
Q9
NDS331N
460 mW
DS10
VCC3V3
R392
261Ω
0.1W
1%
GND
GPIO_LED_
CENTER
GPIO_LED_
RIGHT
GPIO_LED_0
GPIO_LED_
LEFT
1
2
1
2
1
2
1
2
1
3
2
Q30
NDS331N
460 mW
DS35
VCC3V3
R544
261Ω
0.1W
1%
GND
1
2
1
2
Table 1-28: User LED Connections to XC7Z045 SoC U1 XC7Z045 SoC (U1) Pin Net Name
I/O Standard
LED Reference
Y21
GPIO_LED_LEFT
LVCMOS25
DS8
G2
GPIO_LED_CENTER
LVCMOS25
DS9
W21
GPIO_LED_RIGHT
LVCMOS25
DS10
A17
GPIO_LED_0
LVCMOS25
DS35
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Feature Descriptions
User Pushbuttons
[Figure 1-3, callout 23]
Figure 1-27 shows the user pushbutton circuits.
Table 1-29 lists the user pushbutton connections to XC7Z045 SoC U1.
X-Ref Target - Figure 1-27
Figure 1-27: User Pushbuttons
VADJ
GPIO_SW_LEFT
R66
4.7 kΩ
0.1 W
5%
GND
4
3
2
1
SW7
VCC1V5_PL
GPIO_SW_CENTER
R72
4.7 kΩ
0.1 W
5%
GND
4
3
2
1
SW9
GPIO_SW_RIGHT
R67
4.7 kΩ
0.1 W
5%
GND
4
3
2
1
SW8
VCC1V5_PL
PL_CPU_RESET
R516
1.00K
1/16 W
1%
GND
1
3
2
1
SW13
VADJ
X22404-022719
Table 1-29: User Pushbutton Connections to XC7Z045 SoC U1 XC7Z045 SoC (U1) Pin Net Name
I/O Standard
Pushbutton Reference
AK25
GPIO_SW_LEFT
LVCMOS25
SW7
K15
GPIO_SW_CENTER
LVCMOS15
SW9
R27
GPIO_SW_RIGHT
LVCMOS25
SW8
A8
PL_CPU_RESET
LVCMOS15
SW13
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Feature Descriptions
GPIO DIP Switch
Figure 1-28 shows the GPIO DIP switch circuit.
Table 1-30 lists the GPIO DIP switch connections to XC7Z045 SoC U1.
User PMOD GPIO Headers
[Figure 1-3, callout 26]
The ZC706 evaluation board GPIO 2 x 6 male headers J57 and J58 support Digilent Pmod Peripheral Modules. J57 pins (IIC_PMOD_[0:7]) are connected to the TI TCA6416APWR I2C expansion port device U16. J58 pins (PMOD1_[0:7]) are connected to the TI TXS0108E 3.3V-to-VADJ level-shifter U40.
See the Digilent website for information on Digilent Pmod Peripheral Modules [Ref 36].
Information about the TCA641APWR and TXS0108E devices is available at the Texas Instruments website [Ref 27].
X-Ref Target - Figure 1-28
Figure 1-28: GPIO DIP Switch
Table 1-30: GPIO DIP Switch Connections to XC7Z045 SoC at U1
XC7Z045 S0C (U1) Pin
Net Name
I/O Standard
DIP Switch SW12 Pin
AB17
GPIO_DIP_SW0
LVCMOS25
1
AC16
GPIO_DIP_SW1
LVCMOS25
2
AC17
GPIO_DIP_SW2
LVCMOS25
3
AJ13
GPIO_DIP_SW3
LVCMOS25
4
UG954_c1_27_041113
SDA02H1SBD
SW12
VADJ
8 7
GPIO_DIP_SW0
GPIO_DIP_SW1
R70
4.7 kΩ
0.1 W
5%
R71
4.7 kΩ
0.1 W
5%
1 2
R68
4.7 kΩ
0.1 W
5%
R69
4.7 kΩ
0.1 W
5%
GND
GPIO_DIP_SW2 GPIO_DIP_SW3
6
5
3
4
1
2
1
2
1
2
1
2
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Feature Descriptions
Figure 1-29 shows the user GPIO male pin header circuits.
X-Ref Target - Figure 1-29
Figure 1-29: User GPIO Headers
PMOD1_0_LS
PMOD1_1_LS
PMOD1_2_LS
PMOD1_3_LS
PMOD1_4_LS
PMOD1_5_LS
PMOD1_6_LS
PMOD1_7_LS
PMOD1_0
PMOD1_1
PMOD1_2
PMOD1_3
PMOD1_4
PMOD1_5
PMOD1_6
PMOD1_7
HDR_2X6
VCC3V3
VCCA
A1
A2
A3
A4
A5
A6
A7
A8
OE
VCCB
B1
B2
B3
B4
B5
B6
B7
B8
GND
19
20
18
17
16
15
14
13
12
11
2
4
6
8
10
12
1
3
5
7
9
11
PMOD1_4
PMOD1_5
PMOD1_6
PMOD1_7
PMOD1_0
PMOD1_1
PMOD1_2
PMOD1_3
2
1
3
4
5
6
7
8
9
10
TSSOP_20
TCA6416APWR
U40
U16
GND
GND
UG954_c1_28_031715
R310
DNP
DNP
DNP
R330
0
1/10W
5%
R65
4.7
1/10W
5%
1
2
1
2
1
2
TXS0108E
C105
0.1UF
10V
X5R
C104
0.1UF
10V
X5R
J58
1
2
GND
1
2
GND
GND
PORT_EXPANDER_DDR3_SDA PORT_EXPANDER_DDR3_SCL
NC
IIC_PMOD_0
IIC_PMOD_1
IIC_PMOD_2
IIC_PMOD_3
IIC_PMOD_4
IIC_PMOD_5
IIC_PMOD_6
IIC_PMOD_7
FMC_VADJ_ON_R_B
FMC_LPC_PRSNT_M2C_B
FMC_HPC_PRSNT_M2C_B
FMC_HPC_PG_M2C
XADC_MUX_ADDR0
XADC_MUX_ADDR1
XADC_MUX_ADDR2
PL_PWR_ON_R
HDR_2X6
VCC3V3_PS
VCCP
VCCI
SDA
SCL
ADDR
RESET_B
INT_B
GND
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
2
4
6
8
10
12
1
3
5
7
9
11
IIC_PMOD_4
IIC_PMOD_5
IIC_PMOD_6
IIC_PMOD_7
IIC_PMOD_0
IIC_PMOD_1
IIC_PMOD_2
IICPMOD_3
24
2
23
22
21
3
1
12
VCC3V3_PS
VCC3V3_PS
TCA6416APWR
C97
0.1UF
10V
X5R
C96
0.1UF
10V
X5R
J57
1
2
GND
1
2
GND
GND
GND VADJ
VCC3V3
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Feature Descriptions
Table 1-31 lists the GPIO Header connections to XC7Z045 SoC U1.
See Zynq-7000 SoC Technical Reference Manual (UG585) for information about the PS PJTAG functionality.
Switches
The ZC706 evaluation board includes a power and a configuration (PL PROG_B) switch:
•
Power On/Off slide switch SW1 (callout 27)
•
SW10 (FPGA_PROG_B), active-Low pushbutton (callout 28)
•
PS System Reset Pushbuttons
Power On/Off Slide Switch
[Figure 1-3, callout 27]
The ZC706 evaluation board power switch is SW1. Sliding the switch actuator from the Off to On position applies 12V power from J22 a 6-pin mini-fit connector. Green LED DS22 illuminates when the ZC706 evaluation board power is on. See Power Management for details on the onboard power system.
Table 1-31: GPIO Header Connections to XC7Z045 SoC at U1
TCA6416APWR (U16) PORT: Pin
Net Name
GPIO Header J57 Pin
P00:4
IIC_PMOD_0
J57.1
P01:5
IIC_PMOD_1
J57.3
P02:6
IIC_PMOD_2
J57.5
P03:7
IIC_PMOD_3
J57.7
P04:8
IIC_PMOD_4
J57.2
P05:9
IIC_PMOD_5
J57.4
P06:10
IIC_PMOD_6
J57.6
P07:11
IIC_PMOD_7
J57.8
XC7Z045 SoC (U1) Pin
Net Name
GPIO Header J58 Pin
AJ21
PMOD1_0
J58.1
AK21
PMOD1_1
J58.3
AB21
PMOD1_2
J58.5
AB16
PMOD1_3
J58.7
Y20
PMOD1_4
J58.2
AA20
PMOD1_5
J58.4
AC18
PMOD1_6
J58.6
AC19
PMOD1_7
J58.8
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Feature Descriptions
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J22 on the ZC706 Evaluation Board. The ATX 6-pin connector has a different pinout than J22. Connecting an ATX 6-pin connector into J22 will damage the ZC706 Evaluation Board and void the board warranty.
The ZC706 evaluation kit provides the adapter cable shown in Figure 1-30 for powering the ZC706 board from the ATX power supply 4-pin peripheral connector. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number AZCBL-WH-1109-RA4. For information on ordering this cable, see [Ref 37].
Figure 1-31 shows the power connector J22, power switch SW1 and indicator LED DS22.
Program_B Pushbutton
[Figure 1-3, callout 28]
Switch SW10 grounds the XC7Z045 SoC PROG_B pin when pressed. This action clears the programmable logic configuration. The FPGA_PROG_B signal is connected to XC7Z045 SoC U1 pin Y9.
See 7 Series FPGAs Configuration User Guide, (UG470) for further details on configuring the 7 series FPGAs.
X-Ref Target - Figure 1-30
Figure 1-30: ATX Power Supply Adapter Cable
X-Ref Target - Figure 1-31
Figure 1-31: Power On/Off Switch SW1
UG954_c1_29_041113
To ATX 4-Pin Peripheral Power Connector
To J22 on ZC706 Board
UG954_c1_30_041113
VCC12_P_IN
VCC12_P
R171
2.15kΩ
.1W
1%
INPUT_GND
1
2
3
4
SW1
GND
C568
330 μF
25V
C319
1μF
25V
GND
DS22
5
6
J22
1
2
3
4
5
6
12V
N/C
COM
12V
N/C
COM
INPUT_GND
U18 50Ω
1
3
8
7
6
5
1
2
1
2
1
2
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Figure 1-32 shows SW10.
PS Power-On and System Reset Pushbuttons
Figure 1-33 shows the reset circuitry for the processing system.
Depressing and then releasing pushbutton SW1 causes PS_POR_B_SW to strobe low.
PS_POR_B: This reset is used to hold the PS in reset until all PS power supplies are at the required voltage levels. It must be held Low through PS power-up. PS_POR_B should be generated by the power supply power-good signal.
X-Ref Target - Figure 1-32
Figure 1-32: PROG_B Pushbutton SW10
UG954_c1_31_041113
FPGA_PROG B
VCC3V3
R73
4.7 kΩ
0.1 W
5%
GND
2
1
3
4
SW10
X-Ref Target - Figure 1-33
Figure 1-33: PS Power On and System Reset Circuitry
UG954_c1_32_032916
MAX16025 Dual Voltage Monitor and Sequencer
2 3
6
13
9
4
U8
7
8
TH1
12
11
10
15
17
14
16
5
TH0
TOL
MR_B
EN2
EN1
IN2
IN1
GND
EPAD
CRESET
CDLY2
CDLY1
OUT2
OUT1
RST_B
1
VCC
VCCP1V8
R177
8.06 KΩ
0.1W
1%
R264
10.0 Ω
0.1W
1%
VCCP1V8
R265
10.0 KΩ
0.1W
1%
R149
249Ω
0.1W
1%
R176
8.06 KΩ
0.1W
1%
R256
10.0 KΩ
0.1W
1%
R263
10.0 KΩ
0.1W
1%
R262
10.0 KΩ
0.1W
1%
R261
10.0 K
0.1W
1%
J7
1
2
SW3
1
2
SW2
GND
VCCP1V8
PS_POR_B
PS_SRST_B
C8
DNP
DNP
xxx
C7
0.1 μf
25V
X5R
C6
5600 pF
25V
X5R
GND
VCC3V3_PS
DS1
GND
PS_POR_B_SW PS_SRST_B_SW
1
2
3
J44
VCCP1V8
R266
10.0 KΩ
0.1W
1%
1
2
3
J43
PS_POR_B PS_SRST_B
VCC3V3
C8 = DNP, SRST delay = 35 μS C6 = 5600 pF, POR delay = 22.4 mS
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Feature Descriptions
Depressing and then releasing pushbutton SW3 causes PS_SRST_B_SW (connected to the XC7Z045 SoC U1 dedicated PS Bank 500 pin D21) to strobe low.
PS_SRST_B: This reset is used to force a system reset. It can be tied or pulled High, and can be High during the PS supply power ramps.
See Zynq-7000 SoC Technical Reference Manual (UG585) for information concerning the resets.
FPGA Mezzanine (FMC) Card Interface
[Figure 1-3, callout 30 and 31]
The ZC706 evaluation board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by providing subset implementations of the high pin count (HPC) connector at J37 and low pin count (LPC) version at J5. Both connectors use a 10 x 40 form factor. The HPC connector is populated with 400 pins, while the LPC connector is partially populated with 160 pins. The connectors are keyed so that a mezzanine card, when installed in either of these FMC connectors on the ZC706 evaluation board, faces away from the ZC706 board.
Connector Type:
•
Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
More information about SEAF series connectors is available at the Samtec website [Ref 32]. More information about the VITA 57.1 FMC specification is available at the VITA FMC Marketing Alliance website [Ref 38].
HPC Connector J37
[Figure 1-3, callout 30]
The 400-pin HPC connector defined by the FMC specification (Figure B-2, page 93) provides connectivity for up to:
•
160 single-ended or 80 differential user-defined signals
•
10 GTX transceivers
•
2 GTX clocks
•
4 differential clocks
•
159 ground and 15 power connections
The connections between the HPC connector at J37 and SoC U1 (Table 1-32) implements a subset of this connectivity:
•
34 differential user-defined pairs (34 LA pairs, LA00–LA33)
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Feature Descriptions
•
8 GTX transceivers
•
2 GTX clocks
•
2 differential clocks
•
159 ground and 15 power connections
The ZC706 board V ADJ voltage for the J37 and J5 connectors is determined by the FMC V ADJ power sequencing logic described in the Power Management, page 79.
Note: HPC FMC (J37) GA0 = GA1 = 0 = GND.
Table 1-32 shows the J37 HPC FMC to SoC U1 connections.
Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
A2
FMC_HPC_DP1_M2C_P
(1)
AJ8
B1
NC
N/A
N/A
A3
FMC_HPC_DP1_M2C_N
(1)
AJ7
B4
NC
N/A
N/A
A6
FMC_HPC_DP2_M2C_P
(1)
AG8
B5
NC
N/A
N/A
A7
FMC_HPC_DP2_M2C_N
(1)
AG7
B8
NC
N/A
N/A
A10
FMC_HPC_DP3_M2C_P
(1)
AE8
B9
NC
N/A
N/A
A11
FMC_HPC_DP3_M2C_N
(1)
AE7
B12
FMC_HPC_DP7_M2C_P
(1)
AD6
A14
FMC_HPC_DP4_M2C_P
(1)
AH6
B13
FMC_HPC_DP7_M2C_N
(1)
AD5
A15
FMC_HPC_DP4_M2C_N
(1)
AH5
B16
FMC_HPC_DP6_M2C_P
(1)
AF6
A18
FMC_HPC_DP5_M2C_P
(1)
AG4
B17
FMC_HPC_DP6_M2C_N
(1)
AF5
A19
FMC_HPC_DP5_M2C_N
(1)
AG3
B20
FMC_HPC_GBTCLK1_M2C_P
(1)
AA8
A22
FMC_HPC_DP1_C2M_P
(1)
AK6
B21
FMC_HPC_GBTCLK1_M2C_N
(1)
AA7
A23
FMC_HPC_DP1_C2M_N
(1)
AK5
B24
NC
N/A
N/A
A26
FMC_HPC_DP2_C2M_P
(1)
AJ4
B25
NC
N/A
N/A
A27
FMC_HPC_DP2_C2M_N
(1)
AJ3
B28
NC
N/A
N/A
A30
FMC_HPC_DP3_C2M_P
(1)
AK2
B29
NC
N/A
N/A
A31
FMC_HPC_DP3_C2M_N
(1)
AK1
B32
FMC_HPC_DP7_C2M_P
(1)
AD2
A34
FMC_HPC_DP4_C2M_P
(1)
AH2
B33
FMC_HPC_DP7_C2M_N
(1)
AD1
A35
FMC_HPC_DP4_C2M_N
(1)
AH1
B36
FMC_HPC_DP6_C2M_P
(1)
AE4
A38
FMC_HPC_DP5_C2M_P
(1)
AF2
B37
FMC_HPC_DP6_C2M_N
(1)
AE3
A39
FMC_HPC_DP5_C2M_N
(1)
AF1
B40
NC
N/A
N/A
C2
FMC_HPC_DP0_C2M_P
(1)
AK10
D1
PWRCTL1_FMC_PG_C2M
LVCMOS25
AB20
C3
FMC_HPC_DP0_C2M_N
(1)
AK9
D4
FMC_HPC_GBTCLK0_M2C_P
(1)
AD10
C6
FMC_HPC_DP0_M2C_P
(1)
AH10
D5
FMC_HPC_GBTCLK0_M2C_N
(1)
AD9
C7
FMC_HPC_DP0_M2C_N
(1)
AH9
D8
FMC_HPC_LA01_CC_P
LVCMOS25
AG21
C10
FMC_HPC_LA06_P
LVCMOS25
AG22
D9
FMC_HPC_LA01_CC_N
LVCMOS25
AH21
C11
FMC_HPC_LA06_N
LVCMOS25
AH22
D11
FMC_HPC_LA05_P
LVCMOS25
AH23
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C14
FMC_HPC_LA10_P
LVCMOS25
AG24
D12
FMC_HPC_LA05_N
LVCMOS25
AH24
C15
FMC_HPC_LA10_N
LVCMOS25
AG25
D14
FMC_HPC_LA09_P
LVCMOS25
AD21
C18
FMC_HPC_LA14_P
LVCMOS25
AC24
D15
FMC_HPC_LA09_N
LVCMOS25
AE21
C19
FMC_HPC_LA14_N
LVCMOS25
AD24
D17
FMC_HPC_LA13_P
LVCMOS25
AA22
C22
FMC_HPC_LA18_CC_P
LVCMOS25
W25
D18
FMC_HPC_LA13_N
LVCMOS25
AA23
C23
FMC_HPC_LA18_CC_N
LVCMOS25
W26
D20
FMC_HPC_LA17_CC_P
LVCMOS25
V23
C26
FMC_HPC_LA27_P
LVCMOS25
V28
D21
FMC_HPC_LA17_CC_N
LVCMOS25
W24
C27
FMC_HPC_LA27_N
LVCMOS25
V29
D23
FMC_HPC_LA23_P
LVCMOS25
P25
C30
FMC_HPC_IIC_SCL
N/A
U65.13
D24
FMC_HPC_LA23_N
LVCMOS25
P26
C31
FMC_HPC_IIC_SDA
N/A
U65.12
D26
FMC_HPC_LA26_P
LVCMOS25
R28
C34
GA0 = 0 = GND
N/A
N/A
D27
FMC_HPC_LA26_N
LVCMOS25
T28
C35
VCC12_P
N/A
N/A
D29
FMC_HPC_TCK_BUF
N/A
U23.15
C37
VCC12_P
N/A
N/A
D30
FMC_TDI_BUF
N/A
U23.18
C39
VCC3V3
N/A
N/A
D31
FMC_HPC_TDO_FMC_LPC_TDI
N/A
U32.2
D32
VCC3V3
N/A
N/A
D33
FMC_HPC_TMS_BUF
N/A
U23.17
D34
NC
N/A
N/A
D35
GA1 = 0 = GND
N/A
N/A
D36
VCC3V3
N/A
N/A
D38
VCC3V3
N/A
N/A
D40
VCC3V3
N/A
N/A
E2
NC
N/A
N/A
F1
FMC_HPC_PG_M2C
N/A
U16.16
E3
NC
N/A
N/A
F4
NC
N/A
N/A
E6
NC
N/A
N/A
F5
NC
N/A
N/A
E7
NC
N/A
N/A
F7
NC
N/A
N/A
E9
NC
N/A
N/A
F8
NC
N/A
N/A
E10
NC
N/A
N/A
F10
NC
N/A
N/A
E12
NC
N/A
N/A
F11
NC
N/A
N/A
E13
NC
N/A
N/A
F13
NC
N/A
N/A
E15
NC
N/A
N/A
F14
NC
N/A
N/A
E16
NC
N/A
N/A
F16
NC
N/A
N/A
E18
NC
N/A
N/A
F17
NC
N/A
N/A
E19
NC
N/A
N/A
F19
NC
N/A
N/A
E21
NC
N/A
N/A
F20
NC
N/A
N/A
E22
NC
N/A
N/A
F22
NC
N/A
N/A
E24
NC
N/A
N/A
F23
NC
N/A
N/A
E25
NC
N/A
N/A
F25
NC
N/A
N/A
Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1 (Cont’d)
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
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E27
NC
N/A
N/A
F26
NC
N/A
N/A
E28
NC
N/A
N/A
F28
NC
N/A
N/A
E30
NC
N/A
N/A
F29
NC
N/A
N/A
E31
NC
N/A
N/A
F31
NC
N/A
N/A
E33
NC
N/A
N/A
F32
NC
N/A
N/A
E34
NC
N/A
N/A
F34
NC
N/A
N/A
E36
NC
N/A
N/A
F35
NC
N/A
N/A
E37
NC
N/A
N/A
F37
NC
N/A
N/A
E39
VADJ
N/A
N/A
F38
NC
N/A
N/A
F40
VADJ
N/A
N/A
G2
FMC_HPC_CLK1_M2C_P
LVCMOS25
U26
H1
NC
N/A
N/A
G3
FMC_HPC_CLK1_M2C_N
LVCMOS25
U27
H2
FMC_HPC_PRSNT_M2C_B
N/A
U16.15
G6
FMC_HPC_LA00_CC_P
LVCMOS25
AF20
H4
FMC_HPC_CLK0_M2C_P
LVCMOS25
AE22
G7
FMC_HPC_LA00_CC_N
LVCMOS25
AG20
H5
FMC_HPC_CLK0_M2C_N
LVCMOS25
AF22
G9
FMC_HPC_LA03_P
LVCMOS25
AH19
H7
FMC_HPC_LA02_P
LVCMOS25
AK17
G10
FMC_HPC_LA03_N
LVCMOS25
AJ19
H8
FMC_HPC_LA02_N
LVCMOS25
AK18
G12
FMC_HPC_LA08_P
LVCMOS25
AF19
H10
FMC_HPC_LA04_P
LVCMOS25
AJ20
G13
FMC_HPC_LA08_N
LVCMOS25
AG19
H11
FMC_HPC_LA04_N
LVCMOS25
AK20
G15
FMC_HPC_LA12_P
LVCMOS25
AF23
H13
FMC_HPC_LA07_P
LVCMOS25
AJ23
G16
FMC_HPC_LA12_N
LVCMOS25
AF24
H14
FMC_HPC_LA07_N
LVCMOS25
AJ24
G18
FMC_HPC_LA16_P
LVCMOS25
AA24
H16
FMC_HPC_LA11_P
LVCMOS25
AD23
G19
FMC_HPC_LA16_N
LVCMOS25
AB24
H17
FMC_HPC_LA11_N
LVCMOS25
AE23
G21
FMC_HPC_LA20_P
LVCMOS25
U25
H19
FMC_HPC_LA15_P
LVCMOS25
Y22
G22
FMC_HPC_LA20_N
LVCMOS25
V26
H20
FMC_HPC_LA15_N
LVCMOS25
Y23
G24
FMC_HPC_LA22_P
LVCMOS25
V27
H22
FMC_HPC_LA19_P
LVCMOS25
T24
G25
FMC_HPC_LA22_N
LVCMOS25
W28
H23
FMC_HPC_LA19_N
LVCMOS25
T25
G27
FMC_HPC_LA25_P
LVCMOS25
T29
H25
FMC_HPC_LA21_P
LVCMOS25
W29
G28
FMC_HPC_LA25_N
LVCMOS25
U29
H26
FMC_HPC_LA21_N
LVCMOS25
W30
G30
FMC_HPC_LA29_P
LVCMOS25
R25
H28
FMC_HPC_LA24_P
LVCMOS25
T30
G31
FMC_HPC_LA29_N
LVCMOS25
R26
H29
FMC_HPC_LA24_N
LVCMOS25
U30
G33
FMC_HPC_LA31_P
LVCMOS25
N29
H31
FMC_HPC_LA28_P
LVCMOS25
P30
G34
FMC_HPC_LA31_N
LVCMOS25
P29
H32
FMC_HPC_LA28_N
LVCMOS25
R30
G36
FMC_HPC_LA33_P
LVCMOS25
N26
H34
FMC_HPC_LA30_P
LVCMOS25
P23
G37
FMC_HPC_LA33_N
LVCMOS25
N27
H35
FMC_HPC_LA30_N
LVCMOS25
P24
G39
VADJ
N/A
N/A
H37
FMC_HPC_LA32_P
LVCMOS25
P21
H38
FMC_HPC_LA32_N
LVCMOS25
R21
H40
VADJ
N/A
N/A
Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1 (Cont’d)
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
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Feature Descriptions
LPC Connector J5
[Figure 1-3, callout 31]
The 160-pin LPC connector defined by the FMC specification (Figure B-1, page 92) provides connectivity for up to:
•
68 single-ended or 34 differential user-defined signals
•
1 GTX transceiver
J2
NC
N/A
N/A
K1
NC
N/A
N/A
J3
NC
N/A
N/A
K4
NC
N/A
N/A
J6
NC
N/A
N/A
K5
NC
N/A
N/A
J7
NC
N/A
N/A
K7
NC
N/A
N/A
J9
NC
N/A
N/A
K8
NC
N/A
N/A
J10
NC
N/A
N/A
K10
NC
N/A
N/A
J12
NC
N/A
N/A
K11
NC
N/A
N/A
J13
NC
N/A
N/A
K13
NC
N/A
N/A
J15
NC
N/A
N/A
K14
NC
N/A
N/A
J16
NC
N/A
N/A
K16
NC
N/A
N/A
J18
NC
N/A
N/A
K17
NC
N/A
N/A
J19
NC
N/A
N/A
K19
NC
N/A
N/A
J21
NC
N/A
N/A
K20
NC
N/A
N/A
J22
NC
N/A
N/A
K22
NC
N/A
N/A
J24
NC
N/A
N/A
K23
NC
N/A
N/A
J25
NC
N/A
N/A
K25
NC
N/A
N/A
J27
NC
N/A
N/A
K26
NC
N/A
N/A
J28
NC
N/A
N/A
K28
NC
N/A
N/A
J30
NC
N/A
N/A
K29
NC
N/A
N/A
J31
NC
N/A
N/A
K31
NC
N/A
N/A
J33
NC
N/A
N/A
K32
NC
N/A
N/A
J34
NC
N/A
N/A
K34
NC
N/A
N/A
J36
NC
N/A
N/A
K35
NC
N/A
N/A
J37
NC
N/A
N/A
K37
NC
N/A
N/A
J39
NC
N/A
N/A
K38
NC
N/A
N/A
K40
NC
N/A
N/A
Notes:
1.
No I/O standards are associated with MGT connections.
Table 1-32: J37 HPC FMC Connections to XC7Z045 SoC U1 (Cont’d)
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
J37 FMC
HPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
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•
1 GTX clock
•
2 differential clocks
•
61 ground and 10 power connections
The connections between the HPC connector at J5 and SoC U1 implements a subset of this connectivity:
•
34 differential user-defined pairs (34 LA pairs, LA00–LA33)
•
1 GTX transceiver
•
1 GTX clock
•
2 differential clocks
•
61 ground and 9 power connections
Note: LPC FMC (J5) GA0 = GA1 = 0 = GND.
Table 1-33 shows the FMC LPC connections between J5 and XC7Z045 SoC U1.
Table 1-33: J5 LPC FMC Connections to SoC U1
J5 FMC
LPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
J5 FMC
LPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
C2
FMC_LPC_DP0_C2M_P
(1)
AB2
D1
PWRCTL1_FMC_PG_C2M
LVCMOS25
AB20
C3
FMC_LPC_DP0_C2M_N
(1)
AB1
D4
FMC_LPC_GBTCLK0_M2C_P
(1)
U8
C6
FMC_LPC_DP0_M2C_P
(1)
AC4
D5
FMC_LPC_GBTCLK0_M2C_N
(1)
U7
C7
FMC_LPC_DP0_M2C_N
(1)
AC3
D8
FMC_LPC_LA01_CC_P
LVCMOS25
AF15
C10
FMC_LPC_LA06_P
LVCMOS25
AB12
D9
FMC_LPC_LA01_CC_N
LVCMOS25
AG15
C11
FMC_LPC_LA06_N
LVCMOS25
AC12
D11
FMC_LPC_LA05_P
LVCMOS25
AE16
C14
FMC_LPC_LA10_P
LVCMOS25
AC14
D12
FMC_LPC_LA05_N
LVCMOS25
AE15
C15
FMC_LPC_LA10_N
LVCMOS25
AC13
D14
FMC_LPC_LA09_P
LVCMOS25
AH14
C18
FMC_LPC_LA14_P
LVCMOS25
AF18
D15
FMC_LPC_LA09_N
LVCMOS25
AH13
C19
FMC_LPC_LA14_N
LVCMOS25
AF17
D17
FMC_LPC_LA13_P
LVCMOS25
AH17
C22
FMC_LPC_LA18_CC_P
LVCMOS25
AE27
D18
FMC_LPC_LA13_N
LVCMOS25
AH16
C23
FMC_LPC_LA18_CC_N
LVCMOS25
AF27
D20
FMC_LPC_LA17_CC_P
LVCMOS25
AB27
C26
FMC_LPC_LA27_P
LVCMOS25
AJ28
D21
FMC_LPC_LA17_CC_N
LVCMOS25
AC27
C27
FMC_LPC_LA27_N
LVCMOS25
AJ29
D23
FMC_LPC_LA23_P
LVCMOS25
AJ26
C30
FMC_LPC_IIC_SCL
N/A
U65.15
D24
FMC_LPC_LA23_N
LVCMOS25
AK26
C31
FMC_LPC_IIC_SDA
N/A
U65.14
D26
FMC_LPC_LA26_P
LVCMOS25
AJ30
C34
GA0 = 0 = GND
N/A
N/A
D27
FMC_LPC_LA26_N
LVCMOS25
AK30
C35
VCC12_P
N/A
N/A
D29
FMC_LPC_TCK_BUF
N/A
U23.14
C37
VCC12_P
N/A
N/A
D30
FMC_HPC_TDO_FMC_LPC_TDI
N/A
U31.1
C39
VCC3V3
N/A
N/A
D31
FMC_LPC_TDO_FPGA_TDI
N/A
U31.2
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D32
VCC3V3
N/A
N/A
D33
FMC_LPC_TMS_BUF
N/A
U23.16
D34
NC
N/A
N/A
D35
GA1 = 0 = GND
N/A
N/A
D36
VCC3V3
N/A
N/A
D38
VCC3V3
N/A
N/A
D40
VCC3V3
N/A
N/A
G2
FMC_LPC_CLK1_M2C_P
LVCMOS25
AC28
H1
NC
LVCMOS25
G3
FMC_LPC_CLK1_M2C_N
LVCMOS25
AD28
H2
FMC_LPC_PRSNT_M2C_B
LVCMOS25
U16.14
G6
FMC_LPC_LA00_CC_P
LVCMOS25
AE13
H4
FMC_LPC_CLK0_M2C_P
LVCMOS25
AG17
G7
FMC_LPC_LA00_CC_N
LVCMOS25
AF13
H5
FMC_LPC_CLK0_M2C_N
LVCMOS25
AG16
G9
FMC_LPC_LA03_P
LVCMOS25
AG12
H7
FMC_LPC_LA02_P
LVCMOS25
AE12
G10
FMC_LPC_LA03_N
LVCMOS25
AH12
H8
FMC_LPC_LA02_N
LVCMOS25
AF12
G12
FMC_LPC_LA08_P
LVCMOS25
AD14
H10
FMC_LPC_LA04_P
LVCMOS25
AJ15
G13
FMC_LPC_LA08_N
LVCMOS25
AD13
H11
FMC_LPC_LA04_N
LVCMOS25
AK15
G15
FMC_LPC_LA12_P
LVCMOS25
AD16
H13
FMC_LPC_LA07_P
LVCMOS25
AA15
G16
FMC_LPC_LA12_N
LVCMOS25
AD15
H14
FMC_LPC_LA07_N
LVCMOS25
AA14
G18
FMC_LPC_LA16_P
LVCMOS25
AE18
H16
FMC_LPC_LA11_P
LVCMOS25
AJ16
G19
FMC_LPC_LA16_N
LVCMOS25
AE17
H17
FMC_LPC_LA11_N
LVCMOS25
AK16
G21
FMC_LPC_LA20_P
LVCMOS25
AG26
H19
FMC_LPC_LA15_P
LVCMOS25
AB15
G22
FMC_LPC_LA20_N
LVCMOS25
AG27
H20
FMC_LPC_LA15_N
LVCMOS25
AB14
G24
FMC_LPC_LA22_P
LVCMOS25
AK27
H22
FMC_LPC_LA19_P
LVCMOS25
AH26
G25
FMC_LPC_LA22_N
LVCMOS25
AK28
H23
FMC_LPC_LA19_N
LVCMOS25
AH27
G27
FMC_LPC_LA25_P
LVCMOS25
AF29
H25
FMC_LPC_LA21_P
LVCMOS25
AH28
G28
FMC_LPC_LA25_N
LVCMOS25
AG29
H26
FMC_LPC_LA21_N
LVCMOS25
AH29
G30
FMC_LPC_LA29_P
LVCMOS25
AE25
H28
FMC_LPC_LA24_P
LVCMOS25
AF30
G31
FMC_LPC_LA29_N
LVCMOS25
AF25
H29
FMC_LPC_LA24_N
LVCMOS25
AG30
G33
FMC_LPC_LA31_P
LVCMOS25
AC29
H31
FMC_LPC_LA28_P
LVCMOS25
AD25
G34
FMC_LPC_LA31_N
LVCMOS25
AD29
H32
FMC_LPC_LA28_N
LVCMOS25
AE26
G36
FMC_LPC_LA33_P
LVCMOS25
Y30
H34
FMC_LPC_LA30_P
LVCMOS25
AB29
G37
FMC_LPC_LA33_N
LVCMOS25
AA30
H35
FMC_LPC_LA30_N
LVCMOS25
AB30
G39
VADJ
N/A
N/A
H37
FMC_LPC_LA32_P
LVCMOS25
Y26
H38
FMC_LPC_LA32_N
LVCMOS25
Y27
H40
VADJ
N/A
N/A
Notes:
1.
No I/O standards are associated with MGT connections.
Table 1-33: J5 LPC FMC Connections to SoC U1 (Cont’d)
J5 FMC
LPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
J5 FMC
LPC Pin
Net Name
I/O Standard
XC7Z045
(U1) Pin
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ZC706 Board Power System
The ZC706 board hosts a power system based on the Texas Instruments (TI) UCD90120A power supply sequencer and monitor, and the LMZ31500 and LMZ31700 family voltage regulators.
UCD90120A Description
The UCD90120A is a 12-rail PMBus/I C addressable power-supply sequencer and monitor.
The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. Twenty-six GPIO pins can be used for power supply enables, power-on reset signals, external interrupts, cascading, or other system functions. Twelve of these pins offer pulse width modulation (PWM) functionality. Using these pins, the UCD90120A offers support for margining and general purpose PWM functions.
The TI Fusion Digital Power™ designer software is provided for device configuration. This PC-based graphical user interface (GUI) offers an intuitive interface for configuring, storing, and monitoring all system operating parameters.
LMZ31500 and LMZ31700 Family Regulator Description
The LMZ31520 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 20A load. The LMZ31520 module can accept an input voltage rail between 3V and 14.5V and deliver an adjustable and highly accurate output voltage as low as 0.6V.
The LMZ31506 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 6A load. The LMZ31506 module can accept an input voltage rail between 3V and 14.5V and deliver an adjustable and highly accurate output voltage as low as 0.6V. In older documentation this regulator was known as the TI TPS84621.
The LMZ31710 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 10A load. The LMZ31710 module can accept an input voltage rail between 4.5V and 17V and deliver an adjustable and highly accurate output voltage as low as 0.6V.
These modules only requires two external resistors plus external capacitors to provide a complete power solution. These modules offer the following protection features: thermal shutdown, programmable input under-voltage lockout, output over-voltage protection, short-circuits protection, output current limit, and each allows startup into a pre-biased output.
The LMZ31710 sync input allows synchronization over the 200 kHz to 1,200 kHz switching frequency range and up to six modules can be connected in parallel for higher load currents.
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Table 1-34 shows the ZC706 board TI power system configuration for controller U48.
Table 1-34: ZC706 TI Controller U48 Power System Configuration
Sequencer
Schematic Page
Regulator Type, U#
Voltage Current
Page
Contents
Net Name
U48 PMBus
Addr 101
5 Rails
49
UCD90120A
50
Addr 101, Rail 1
VCCINT
LMZ31520 U42
1.0V
16A
51
Addr 101, Rail 2
VCCAUX, VCC1V8
LMZ31710 U98
1.8V
10A
52
Addr 101, Rail 3
VCC1V5_PL
LMZ31506 U85
1.5V
6A
53
Addr 101, Rail 4
VADJ_FPGA,VADJ
LMZ31506 U86
2.5V
6A
54
Addr 101, Rail 5
VCC3V3_FPGA,VCC3V3
LMZ31710 U15
3.3V
10A
Notes:
ZC706 boards prior to Rev. 2.0 implemented different voltage regulators for VCCINT, VCCAUX/VCC1V8, VCC1V5_PL, VADJ_FPGA/VADJ and VCC3V3_FPGA/VCC3V3. Refer to UG954 v1.3 and earlier, and to the schematic for the particular version of the ZC706 board prior to Rev. 2.0. Notes on ZC706 boards prior to Rev. 2.0:
1.
VCCINT is implemented utilizing 2xLMZ22008 8A components (U42, U43) in parallel which provides 16A capability.
2.
The 1.8V rails are supplied from a LMZ22010 10A component (U98).
3.
VCC1V5_PL and the 2.5V rails are supplied from TPS84621 6A components (U85, U86).
4.
The 3.3V rails are supplied from a LMZ22010 10A component (U15).
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Figure 1-34 shows the power system for UCD90120A U48 controller.
X-Ref Target - Figure 1-34
Figure 1-34: ZC706 TI UCD90120A Controller U48 Power System
Sense Connected
at Point of Load
GPIO (out)
FPWM (out)
ADC (in)
ADC (in)
GPIO (out)
Rail Enable
PWM Margin
Current Sense
Voltage Sense
Low Pwr Select
Vin
EN
FB
Vout
12V Input
Filter
Bulk Filter Caps
Low Power || Radj Low = 1.0V (Default) High = 0.9V
V
Input
Filter
Bulk Filter Caps
V
Vin
EN
FB
Vout
Vin
EN
FB
Vout
Vin
EN
FB
Vout
Vin
EN
FB
Vout
LMZ31520
U42
LMZ31710
U98
Rail Enable
PWM Margin
Current Sense
Voltage Sense
Rail Enable
PWM Margin
Current Sense
Voltage Sense
Rail Enable
PWM Margin
Current Sense
Voltage Sense
Rail Enable
PWM Margin
Current Sense
Voltage Sense
I0B
I1B
I2B
I3B
S[1:0]
YB
FMC_ADJ_SEL[1:0]
GPIO (out)
FPWM (out)
ADC (in)
ADC (in)
GPIO (out)
FPWM (out)
ADC (in)
ADC (in)
GPIO (out)
FPWM (out)
ADC (in)
ADC (in)
GPIO (out)
GPIO (out)
FPWM (out)
ADC (in)
ADC (in)
FMC_ADJ_SEL[1:0]
VCCINT 1.0V
UCD90120A Controller U48
VCCINT 1.0V Nom.
VCCAUX 1.8V Nom.
Input
Filter
Bulk Filter Caps
V
LMZ31506
U85
VCC1V5_PL 1.5V Nom.
Input
Filter
Bulk Filter Caps
V
LMZ31506
U86
VADJ_FPGA 2.5V Nom.
Input
Filter
Bulk Filter Caps
V
LMZ31710
U15
VCC3V3 FPGA 3.3V Nom.
U66
Dual 4-to-1 Mux
Sense Connected
at Point of Load
VCCAUX 1.8V
VCC1V8 1.8V
Sense Connected
at Point of Load
VADJ_FPGA 2.5V
VADDJ 2.5V
Sense Connected
at Point of Load
VCC3V3 FPGA 3.3V
VCC3V3 3.3V
Sense Connected
at Point of Load
VCC1V5_PL 1.5V
[ 1 0 ]
0
0
1
1
0
1
0
1
UG954_c1_33_041615
Notes:
1. Capacitors labeled Cf are bulk filter capacitors.
2. Voltage Sense is connected a point of load.
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The LMZ31520, LMZ31506, and LMZ31710 adjustable voltage regulators have their output voltage set through an external resistor. The regulator topology on the ZC706 board permits the TI UCD90120A module to monitor rail voltage and current. Voltage margining at +5% and -5% is also implemented.
Each voltage regulator’s external V OUT setting resistor is calculated and implemented as if the regulator is stand-alone. The TI UCD90120A module has two ADC inputs allocated per voltage rail, one input for the remote voltage sense connection, the other for the current sense resistor op amp output voltage connection. The TI UCD90120A ADC full scale input is 2.5V. The remote voltage feedback is scaled to approximately 2V if it exceeds 2V, that is, the V CCO_VADJ rail for the 2.5V and 3.3V modes, and the FPGA_3V3 rail also at 3.3V are
resistor-attenuated to scale the remotely sensed voltage at a ratio of 0.606 to give approximately 2V at the ADC input pin for a 3.3V remote sense value. Rails below 2V are not scaled.
Each rail’s current sense op amp has its gain set to provide approximately 2V maximum at the TI UCD90120A ADC input pin when the rail current is at its expected maximum current level, as can be seen in the U48 controller power system figure (Figure 1-34).
The TI UCD90120A module has an assignable group of GPIO pins with PWM capability. Each controller “channel” has a PWM GPIO pin wired to the associated voltage regulator V ADJ pin. The external V OUT setting resistor is also wired to this pin. The PWM GPIO pin is configured in 3-state mode. This pin is not driven unless a Margin command is executed. The Margin command is available within the TI Fusion Digital Power™ designer software.
During the margin-High or Low operation, the PWM GPIO pin drives a voltage into the voltage regulator V ADJ pin, which causes a slight voltage change resulting in the regulator V OUT moving to the margin +5% or -5% voltage commanded.
XADC Power System Measurement
The ZC706 board XADC interface includes power system voltage and current measuring capability. The V CCINT and V CCAUX rail voltages are measured using the XADC internal voltage measurement capability. Other rails are measured through an external Analog Devices ADG707BRU multiplexer U6. Each rail has a separate TI INA333 op amp strapped across its series current sense resistor Kelvin terminals. This op amp has its gain adjusted to give approximately 1V at the expected full scale current value for the rail.
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Figure 1-35 shows the XADC external MUX block diagram.
See Table 1-35 which lists the ZC706 XADC power system voltage and current measurement details for the external MUX U6.
X-Ref Target - Figure 1-35
Figure 1-35: XADC External MUX Block Diagram
Notes:
1.
_XADC_P/N = Remote Voltage Sense
2.
_XADC_CS_P/N = Current Sense From OP Amp
UG954_c1_34_041113
U1
U6
3.3 Scaled to 0.825V
ADG707BRU
Bank 35
ADIP L13
DA
DB
10PF
A0
A1
A2
3.01K
1.00K
GND
49.9
49.9
A[2:0]
P14 17
P15 18
P16 19
S1A/B
S2A/B
S3A/B
S4A/B
S5A/B
S6A/B
S7A/B
S8A/B
VCC3V3_FPGA_SENSE_P
VCC3V3_FPGA_XADC_P
VCC3V3_FPGA_SENSE_N
VADJ 2.5V Scaled to 0.625V
3.01K
1.00K
GND
VCC3V3_FPGA_SENSE_P
VCC3V3_FPGA_XADC_P
VCC3V3_FPGA_SENSE_N
Scaled to 0.75V
3.01K
1.00K
GND
VCC3V3_FPGA_SENSE_P
VCC3V3_FPGA_XADC_P
VCC3V3_FPGA_SENSE_N
VCCINT_XADC_CS_P/N
VCCAUX_XADC_CS_P/N
VCC1V5_PL_XADC_P/N
VCC1V5_PL_XADC_CS_P/N
VADJ_FPGA_XADC_P/N
VADJ_FPGA_XADC_CS_P/N
VCC3V3_PL_XADC_P/N
VCC3V3_PL_XADC_CS_P/N
AD1N K13
U16
XC7Z045
TCA6416APWR
12C Port
Expander
Table 1-35: XADC Measurements through MUX U6
Meas.
Type
Rail Name
Current
Range
Isense Op Amp
Schematic Net Name
8-to-1 MUX U6
MUX A[2:0]
Reference
Designator
Gain
Vo Range
Pin
Num
Pin
Name
V
VCCINT
NA
NA
NA
NA
XADC INTERNAL
NA
NA
NA
I
VCCINT CS
0A-8A
U69
20
0V-0.8V
VCCINT_XADC_CS_P
19
S1A
000
VCCINT_XADC_CS_N
11
S1B
V
VCCAUX
NA
NA
NA
NA
XADC INTERNAL
NA
NA
NA
I
VCCAUX CS
0A-4A
U68
50
0V-1V
VCCAUX_XADC_CS_P
20
S2A
001
VCCAUX_XADC_CS_N
10
S2B
V
VCC1V5_PL
NA
VCC1V5_PL REMOTE SENSE DIVIDED
TO DELIVER 0.75V ON
VCC1V5_PL_XADC_P
VCC1V5_PL_XADC_P
21
S3A
010
VCC1V5_PL_SENSE_N
9
S3B
I
VCC1V5_PL CS
0A-2A
U67
100
0V-1V
VCC1V5_PL_XADC_CS_P
22
S4A
011
VCC1V5_PL_XADC_CS_N
8
S4B
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Feature Descriptions
Power Management
[Figure 1-3, callout 32]
The ZC706 board uses power regulators and a PMBus-compliant system controller from Texas Instruments to supply core and auxiliary voltages. The Texas Instruments Fusion Digital Power graphical user interface is used to monitor the voltage and current levels of the board power modules.
The PCB layout and power system design meet the recommended criteria described in Zynq-7000 SoC PCB Design and Pin Planning Guide (UG933).
The ZC706 evaluation board power distribution diagram is shown in Figure 1-36.
V
VADJ_FPGA
NA
VADJ_FPGA 2.5V REMOTE SENSE DIVIDED TO DELIVER 0.625V ON
VADJ_FPGA_XADC_P
VADJ_FPGA_XADC_P
23
S5A
100
VADJ_FPGA_SENSE_N
7
S5B
I
VADJ_FPGA CS
0A-2A
U70
100
0V-1V
VADJ_FPGA_XADC_CS_P
24
S6A
101
VADJ_FPGA_XADC_CS_N
6
S6B
V
VCC3V3_FPGA
NA
VCC3V3_FPGA REMOTE SENSE DIVIDED TO DELIVER 0.825V ON
VCC3V3_FPGA_XADC_P
VCC3V3_FPGA_XADC_P
25
S7A
110
VCC3V3_FPGA_SENSE_N
5
S7B
I
VCC3V3_FPGA CS
0A-2A
U97
100
0V-1V
VCC3V3_FPGA_XADC_CS_P
26
S8A
111
VCC3V3_FPGA_XADC_CS_N
4
S8B
Table 1-35: XADC Measurements through MUX U6 (Cont’d)
Meas.
Type
Rail Name
Current
Range
Isense Op Amp
Schematic Net Name
8-to-1 MUX U6
MUX A[2:0]
Reference
Designator
Gain
Vo Range
Pin
Num
Pin
Name
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The ZC706 evaluation board uses power regulators and PMBus compliant PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in Table 1-36.
X-Ref Target - Figure 1-36
Figure 1-36: Onboard Power Regulators
Switching Module VCC1V8/VCCAUX 1.8V @ 10A U98 p. 51
Switching Module
VCC1V5_PL 1.5V @ 6A
U85
p. 52
Switching Module VADJ/VADJ _FPGA 2.5V @ 6A U96 p. 53
Switching Module VCC3V3/VCC3V3_FPGA 3.3V @ 10A U15 p. 54
Linear Regulator
MGTVCCAUX 1.8V @ 3A
U95
p. 57
Linear Regulator
VCC2V5 2.5V @ 1.5A
U19
p. 57
Linear Regulator
MGTAVCC 1.0V @ 3A
U93
p. 57
Linear Regulator
MGTAVTT 1.2V @ 3A
U94
p. 57
Linear Regulator
VCCAUX_IO 2.0V @ 3A
U92
p. 57
Source/Sink Regulator VTTDDR_PL 0.75V @ 3A U28
p. 56
Source/Sink Regulator VTTDDR_PS 0.75V @ 0.5A (3A Max) U27 p. 56
Switching Module
VCCINT 1.00V @ 16A
Power Controller 1
PMBus 0x65
Note: Page numbers reference the pages
on schematic 0381513
12V
PWR
Jack
J22
U42
p. 50
U48
p. 49
p. 48
Switching Dual VCC1V5_PS 1.5V @ 2.5A U104
p. 55
Switching Dual
VCCPINT 1.0V @ 1.5A
U104
p. 55
Switching Dual VCC3V3_PS 3.3V @ 2.5A U105
p. 55
Switching Dual
VCCP1V8 1.8V @ 1.5A
U105
p. 55
Linear Regulator V33D_CTL1 3.3V @ 0.25A U20
p. 49
Switching Regulator
VCC5V0 5.0V @ 2A
U44
p. 56
UG954_c1_35_031615
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Feature Descriptions
VADJ Voltage Control
The V ADJ rail is set to 2.5V. When the ZC706 evaluation board is powered on, the state of the FMC_VADJ_ON_B signal wired to header J18 is sampled by the TI UCD90120A controller U48. If a jumper is installed on J18 signal FMC_VADJ_ON_B is held Low, and the TI controller U48 energizes the V ADJ rail at power on.
Table 1-36: Onboard Power System Devices
Device Type
Reference
Designator
Description
Power Rail
Net Name
Power Rail
Voltage
Schematic
Page
UCD90120A
U48
PMBus Controller, PMBus Addr = 101
49
LMZ31520RLG
U42
16A 0.6 - 3.6V Adj. Switching Regulator
VCCINT
1.00V
50
LMZ31710RVQ
U98
10A 0.6V - 5.5V Adj. Switching Regulator
VCCAUX
1.80V
51
LMZ31506RUQ
U85
6A 0.6V - 5.5V Adj. Switching Regulator
VCC1V5_PL
1.50V
52
LMZ31506RUQ
U86
6A 0.6V - 5.5V Adj. Switching Regulator
VADJ_FPGA
2.50V
53
LMZ31710RVQ
U15
10A 0.6V - 5.5V Adj. Switching Regulator
VCC3V3_FPGA
3.30V
54
TPS54291PWP
(Dual Output)
U104
2.5A 0.8V - 10V Adj. Switching Regulator
VCCPINT
1.00V
55
2.5A 0.8V - 10V Adj. Switching Regulator
VCC1V5_PS
1.50V
55
TPS54291PWP
(Dual Output)
U105
2.5A 0.8V - 10V Adj. Switching Regulator
VCCP1V8
1.80V
55
2.5A 0.8V - 10V Adj. Switching Regulator
VCC3V3_PS
3.30V
55
TPS51200DR
U27
3A Push/Pull Tracking Regulator
VTTDDR_PS
0.75V
56
TPS51200DR
U28
3A Push/Pull Tracking Regulator
VTTDDR_SODIMM
0.75V
56
TPS74901RGW
U92
3A 0.8V - 3.6V Adj. Linear Regulator
VCCAUX_IO
2.00V
57
TPS74901RGW
U93
3A 0.8V - 3.6V Adj. Linear Regulator
MGTAVCC
1.00V
57
TPS74901RGW
U94
3A 0.8V - 3.6V Adj. Linear Regulator
MGTAVTT
1.20V
57
TPS74901RGW
U95
3A 0.8V - 3.6V Adj. Linear Regulator
MGTVCCAUX
1.80V
57
TL1963A
U19
1.5A 1.21V - 3.3V Adj. Linear Regulator
VCC2V5
2.50V
57
TPS79433
U20
0.25A 3.3V Fixed Linear Regulator
V33D_CTL1
3.30V
49
LMZ31704RVQ
U44
2A 0.6V - 5.5V Adj. Switching Regulator
VCC5V0
5.00V
56
Notes:
1.
VCCINT max. current is 16A
2.
VCCBRAM 1.0V is also sourced from the Vccint rail
3.
VCC1V8 1.80V is also sourced from the Vccaux rail
4.
VADJ (1.80V/2.50V/3.30V) for the FMC connectors is also sourced from the Vadj_fpga rail
5.
VCC3V3 3.30V is also sourced from the Vcc3v3_fpga rail
6.
Paralleled dual LMZ22008TZ (U42/U43) 8A 0.8V - 6V Adj. Switching Regulators on ZC706 board versions prior to Rev. 2.0
7.
LMZ22010TZ (U98 VCCAUX, U15 VCC3V3_FPGA) 10A 0.8 - 6V Adj. Switching Regulators on ZC706 board versions prior to Rev. 2.0
8.
LMZ12002TZ U44 2A 0.8 - 6V Adj. Switching Regulator on ZC706 board versions prior to Rev. 2.0
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Feature Descriptions
Because the rail turn on decision is made at power on time based on the presence of the J18 jumper, removing the jumper at J18 after the board is powered up does not affect the 2.5V power delivered to the V ADJ rail and it remains on.
A jumper installed at J18 is the default setting.
In this mode the user can control when to turn on V ADJ and to which voltage level (1.8V, 2.5V, 3.3V). With V ADJ off the XC7Z045 SoC still configures and has access to the TI controller PMBUS along with the FMC_VADJ_ON_B signal. The combination of these allows the user to develop code to command the V ADJ rail to be set to something other than the default setting of 2.5V. Once the new V ADJ voltage level has been programmed into TI controller U48, the FMC_VADJ_ON_B signal can be driven low by the user logic and the V ADJ rail comes up at the new V ADJ voltage level. Installing a jumper at J18 after a ZC706 board powers up in the V ADJ off (no jumper on J18 at ZC706 power up) mode turns on the V ADJ rail.
The FMC_VADJ_ON_B signal is connected to the TCA6416APWR I C port expander U16 pin 13 (see Figure 1-29). The XC7Z045 SoC is thus able to drive the FMC_VADJ_ON_B signal by writing to the I²C port expander U16.
The I C port expander IIC_PORT_EXPANDER SDA/SCL bus is wired to the PCA9548ARGER I C U65 bus switch (see I2C Bus, page 55).
Documentation describing PMBUS programming for the UCD90120A power controller is available at the website [Ref 27].
SoC Programmable Logic (PL) Voltage Control
All PL and PS power rails are enabled by default. When the ZC706 board is powered on, the state of the PL_PWR_ON signal wired to 2-pin header J66 is sampled by the TI UCD90120A controller U48. If a jumper is not installed on J66, signal PL_PWR_ON is held high, and the TI controller U48 energizes all the PL and PS power rails.
Because the rail turn on decision is made at power on time based on the presence of the J66 jumper, installing the jumper at J66 after the board is powered up does not affect power delivered to the any PS or PL rails, all rails remain on.
A jumper not installed at J66 is the default setting.
If a jumper is installed on J66 when the ZC706 board is powered on, signal PL_PWR_ON is held low, and the ZC706 board does not energize the PL side power rails at power on.
Monitoring Voltage and Current
Voltage and current monitoring and control are available for selected power rails through Texas Instruments' Fusion Digital Power Designer graphical user interface. The onboard TI power controller (U48 at address 101) is accessed through the PMBus connector J4, which is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO), which can be ordered from the Texas Instruments website [Ref 28] and
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associated TI Fusion Digital Power Designer GUI (downloadable from the TI site [Ref 29]. This is the simplest and most convenient way to monitor the voltage and current values for the power rails listed in Table 1-37.
In the table, the Power Good (PG) On Threshold is the setpoint at or above which the particular rail is deemed "good". The PG Off Threshold is the setpoint at or below which the particular rail is no longer deemed "good". The controller internally OR's these per rail PG conditions together and drives an output PG pin high only if all active rail PG states are "good". The On and Off Delay and parameters are relative to when the board power on-off slide switch SW12 is turned on and off.
Table 1-37 Power Rail Specifications for UCD90120A PMBus controller at Address 101 defines the voltage and current values for each power rail controlled by the UCD90120A U48.
IMPORTANT: In Table 1-37, the values defined in the Shutdown columns are the voltage and current thresholds that cause the regulator to shut down if the value is exceeded.
The ZC706 power system rail turn on timing is not strictly controlled through the Turn On Delay shown in Table 1-37. The Table 1-37 Turn On Delay delay values are applied after the preceding rail has reached 90% of its nominal voltage. See Table 1-38 for rail turn on dependency details.
Table 1-37: Power Rail Specifications for UCD90120A PMBus Controller at Address 101
Device
Address
Rail
Nominal
Voltage
Power
Good
On
Power
Good
Off
Turn
On
Delay
(ms)
Turn
Off
Delay
(ms)
Shutdown
Over
Voltage
Over
Current
UCD90120A
U48
101d
1
VCCINT
1.000
0.900
0.850
0.0
25.0
1.150
11.50
2
VCCAUX
1.800
1.620
1.530
5.0
20.0
2.070
6.91
3
VCC1V5_PL
1.500
1.350
1.275
5.0
10.0
1.725
3.50
4
VADJ_FPGA
2.500
2.250
2.125
5.0
5.0
2.875
3.50
5
VCC3V3_FPGA
3.300
2.970
2.805
5.0
15.0
3.795
6.91
Notes:
1.
The values defined in these columns are the voltage and current thresholds that cause the regulator to shut down if the value is exceeded.
2.
See Table 1-39 for rail turn on dependency details.
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Feature Descriptions
Cooling Fan
The XC7Z045 SoC cooling fan connector is shown in Figure 1-37.
When V ADJ is modified from a default of 2.5V to 1.8V or a lower V ADJ setting, the SoC U1 cooling fan turns off. Transistor Q1 is used to switch on the fan and has a max VGS of 2V, hence the fan is not guaranteed to work at 1.8V or lower V ADJ, setting. See [Ref 16].
The fan turns on when the ZC706 is powered up due to pull-up resistor R369. The SM_FAN_PWM and SM_FAN_TACH signals are wired to XC7Z045 SoC U1 pins AB19 and
Table 1-38: Power Rail Sequence On Dependencies for UCD90120A PMBus Controller at Address 101
Device
Address
Rail
Nominal
Voltage
Turn On Order
Turn On Timing
UCD90120A
101d
1
VCCINT
1.000
1
Turn on at board power-on
2
VCCAUX
1.800
2
5ms after VCCINT hits 90%
5
VCC3V3_FPGA
3.300
3
5ms after VCCAUX hits 90%
3
VCC1V5_PL
1.500
4
5ms after VCC3V3 hits 90%
4
VADJ_FPGA
2.500
5
5ms after VCC1V5_PL hits 90%
X-Ref Target - Figure 1-37
Figure 1-37: Cooling Fan Circuit
SM FAN TACH
SM FAN PWM
R279
10.0K
1/10W
1%
R278
10.0K
1/10W
1%
1
2
1
2
2
4
1
3
R190
4.75K
1/10W
1%
Q1
1.3W
NDT3055L
VADJ
GND
GND
J61
Keyed Fan Header
VCC12_P
R369
1.00K
1/16W
1%
1
2
1
2
D2
MM3Z2V7B
2.7V
460MW
2
1
D1
DL4148
100V
460MW
22_11_2032
1
2
1
2
3
UG954_c1_36_073013
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Feature Descriptions
AA19 respectively, enabling the user to implement their own fan speed control IP in the SoC PL logic.
More information about the power system components used by the ZC706 evaluation board are available from the Texas Instruments digital power website [Ref 33].
XADC Analog-to-Digital Converter
[Figure 1-3, callout 33]
The XC7Z045 SoC provides an Analog Front End XADC block. The XADC block includes a dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) for details on the capabilities of the analog front end. Figure 1-38 shows the XADC block diagram.
X-Ref Target - Figure 1-38
Figure 1-38: XADC Block Diagram
XC7Z020
AP SoC
U1
VAUX0N
VAUX0P
VAUX8N
VAUX8P
XADC_VREF (1.25V)
VREFN
VCCADC
GNDADC
VN
VP
DXP
DXN
UG8954_c1_37_041715
100Ω
1 nF
100Ω
100Ω
1 nF
100Ω
To
Header
J63
Dual Use IO
(Analog/Digital)
100Ω
1 nF
100Ω
To
Header
J63
100 nF
XADC_AGND
REF3012
U38
Out In
Gnd
J52
XADC_AGND
To Header J63
10 μF
Ferrite Bead
Ferrite Bead
J13
J12
Star Grid
Connection
J54
XADC_VCC
XADC_AGND
GND
VREFP
XADC_VREFP
ADP123
U14
Out In
Gnd
XADC_AGND
10 μF
XADC_VCC Header J40
100 nF
XADC_AGND
To J54
XADC_VCC
J53
Ferrite Bead
VCCAUX
VCC5V0
10
μF
XADC_VCC5V0 To Header J63
1.8V 150 mV max
J14
Close to
Package Pins
Close to
Package Pins
1
2
3
1
2
3
1
2
3
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Feature Descriptions
The ZC706 evaluation board supports both the internal XC7Z045 SoC sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available.
Jumper J52 can be used to select either an external voltage reference (VREF) or on-chip voltage reference for the analog-to-digital converter.
For external measurements an XADC header (J63) is provided. This header can be used to provide analog inputs to the XC7Z045 SoC's dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0], VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.
A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-39 shows the XADC header connections.
Table 1-39 describes the XADC header J40 pin functions.
X-Ref Target - Figure 1-39
Figure 1-39: XADC Header (J63)
UG954_c1_38_041113
XADC_VP
XADC_VAUX0N
XADC_VAUX8P
XADC_DXN
XADC_VCC_HEADER
XADC_VN
XADC_VAUX0P
XADC_VAUX8N
XADC_DXP
XADC_VREF
XADC_GPIO_0
XADC_GPIO_2
XADC_GPIO_1
XADC_GPIO_3
J63
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
GND XADC_AGND
XADC_AGND
XADC_VCC5V0
VCC1V5_PL
Table 1-39: XADC Header J63 Pinout
Net Name
J63 Pin
Number
Description
VN, VP
1, 2
Dedicated analog input channel for the XADC.
XADC_VAUX0P, N
3, 6
Auxiliary analog input channel 0. Also supports use as I/O inputs when anti alias capacitor is not present.
XADC_VAUX8N, P
7, 8
Auxiliary analog input channel 8. Also supports use as I/O inputs when anti alias capacitor is not present.
DXP, DXN
9, 12
Access to thermal diode.
XADC_AGND
4, 5, 10
Analog ground reference.
XADC_VREF
11
1.25V reference from the board.
XADC_VCC5V0
13
Filtered 5V supply from board.
XADC_VCC_HEADER
14
Analog 1.8V supply for XADC.
VCC1V5_PL
15
VCCO supply for bank which is the source of DIO pins.
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Feature Descriptions
GND
16
Digital Ground (board) Reference
XADC_GPIO_3, 2, 1, 0
19, 20, 17,
18
Digital I/O. These pins should come from the same bank. These IOs should not be shared with other functions because they are required to support three-state operation.
Table 1-39: XADC Header J63 Pinout (Cont’d)
Net Name
J63 Pin
Number
Description
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Appendix A
Default Switch and Jumper Settings
The default switch and jumper settings for the ZC706 evaluation board are provided in this appendix.
Switches
[Figure 1-3, callout 24]
Default switch settings are listed in Table A-1. The locations of the ZC706 jumper headers called out in Table A-2 are shown in Figure A-1.
Table A-1: Default Switch Settings
Switch
Function
Default
Selects
Figure 1-3
Callout
SW1
Board main power On-Off Slide Switch
OFF
Delivered in OFF position
27
SW4
2-pole SPST DIP Switch, JTAG mode select signals JTAG_SEL_[1:2]
10
JTAG = cable connector J3
34
SW11
5-pole DPDT DIP Switch, PS Boot Mode select signals MIO[6:2]_SELECT
All Down
JTAG flat cable header J3
29
SW12
4-pole SPST DIP Switch, user signals GPIO_DIP_SW[0:3], poles [1:4]
All OFF
All = 0 (4.7K p/d to GND)
24
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Jumpers
Jumpers
[Figure 1-3, callout 24]
Default jumper positions are listed in Table A-2.
Table A-2: Default Jumper Settings
Jumper
Callout
Jumper
Function
Default Jumper
Position
Option Selected
Schematic
0381513
Page
HDR_1 X 2
1
J6
J65
SoC U1 Bank 0 CFGBVS pin V9 logic 0/1 Select
(call out #1 applies to this, too): J65 is an INIT_B (pin 1) and DONE (pin 2) test header
OPEN
OPEN
CFGBVS pin V9 = 1
N/A
3
3
2
J7
U8 MAX16025 POR Device Reset MR_B pin 13 logic 0/1 Select
OPEN
U8 MR_B pin 13 = 1
15
3
J8
JTAG Header J62 pin 2 can be connected to 3.3V
OPEN
J62 pin 2 is NC
16
4
J9
U51 Ethernet PHY CONFIG2 pin 2 1K pull-down to logic 0 (GND)
1-2
U51 pin 2 CONFIG2 = 0
5
J10
U12 USB3320 2.0 Host/OTG or Device Select Header
1-2
HOST source VBUS power (from U22)
31
6
J11
U12 USB3320 2.0 RESET Header
OPEN
U12 not held in RESET
31
7
J12
U38 REF3012 VREF XADC_AGND-to-GND L3 inductor bypass
OPEN
L3 not bypassed
35
8
J13
U38 REF3012 VREF XADC_AGND-to-GND Select Header
1-2
XADC_AGND connected to GND
35
9
J14
XADC circuit VCC5V0 sources XADC_VCC5V0 Select Header
1-2
XADC_VCC5V0 = filtered (L1) VCC5V0
35
10
J15
ARM PJTAG Header J64 pin 2 can be connected to VADJ
OPEN
J64 pin 2 is NC
39
11
J17
SPF+ P2 pin 3 SFP_TX_DISABLE_TRANS logic 0/1 Select Header
OPEN
SPF+ P2 SFP TX is enabled (P2 pin 3 = 1)
41
12
J18
FMC_VADJ_ON_B Select Header
1-2
FMC VADJ enabled (U48 UCD90120A pin 37 = logic
0)
49
13
J19
PCIe® Lane Width Select Header
3-4
4-Lane PCIe selected
42
14
J66
PL_PWR_ON Header
OPEN
PL Power enabled (U48 UCD90120A pin 24 = logic 1)
49
15
J69
XADC Power System Vccint CS OpAmp U69 Gain Select Header
OPEN
U69 Current Sense OpAmp Gain = 10
45
16
J70
MIO Select Header MIO2 (Note: DIP SW11 pole 1 affects this signal)
1-2
QSPI0_IO0 = MIO2_SELECT
15
17
J71
MIO Select Header MIO3 (Note: DIP SW11 pole 2 affects this signal)
1-2
QSPI0_IO1 = MIO3_SELECT
15
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Jumpers
18
J72
MIO Select Header MIO4 (Note: DIP SW11 pole 3 affects this signal)
1-2
QSPI0_IO4 = MIO2_SELECT
15
19
J73
MIO Select Header MIO5 (Note: DIP SW11 pole 4 affects this signal)
1-2
QSPI0_IO5 = MIO2_SELECT
15
20
J74
MIO Select Header MIO6 (Note: DIP SW11 pole 5 affects this signal)
1-2
QSPI0_CLK = MIO6_SELECT
15
HDR_1 X 3
21
J43
PS_SRST_B Select Header
1-2
PS_SRST_B = PS_SRST_B_SW (MAX16025 U8 pin 10)
15
22
J44
PS_POR_B Select Header
1-2
PS_POR_B = PS_POR_B_SW (MAX16025 U8 pin 11)
15
23
J45
U51 Ethernet PHY CONFIG3 pin 3 1K pull-up to 1.8V or 1 KΩ pull-down to GND Select Header
1-2
U51 pin 3 CONFIG3 = 1 (p/u to 1.8V)
29
24
J46
U51 Ethernet PHY CONFIG2 pin 2 tie to 1.8V or LED0 Select Header
OPEN
J9 sets U51 pin 2 CONFIG2 condition
29
25
J47
U51 Ethernet PHY CONFIG3 pin 3 LED1 or LED0 Select Header
OPEN
No connection to LED0 or LED1, J45 sets U51 pin 3 CONFIG3 condition
29
26
J48
U12 USB3320 2.0 MODE Select Header
2-3
HOST/OTG Mode selected
31
27
J49
USB 2.0 Micro-B connector J2 ID pin 4 function Select Header
1-2
J2 ID pin 4 connected to USB3320 U12 pin 23 ID
31
28
J50
USB_VBUS_SEL 1uF/120 uF capacitor to GND Select Header
2-3
USB_VBUS_SEL net has 120 uF to GND
31
29
J51
USB 2.0 Micro-B connector J2 ID shield pins connection Select Header
1-2
J2 shield pins to GND
31
30
J52
XADC_VREFP source Select Header
1-2
XADC_VREFP = XADC_VREF
35
31
J53
XADC_VCC source Select Header
1-2
XADC_VCC = VCCAUX 1.8V
35
32
J54
U38 REF3012 VREF Vin Select Header
2-3
U38 powered by XADC_VCC (U14 1.85V)
35
33
J55
SPF+ P2 SFP_RS1 BW Select Header
2-3
LOW BW TX selected
41
34
J56
SPF+ P2 SFP_RS0 BW Select Header
2-3
LOW BW RX selected
41
Table A-2: Default Jumper Settings (Cont’d)
Jumper
Callout
Jumper
Function
Default Jumper
Position
Option Selected
Schematic
0381513
Page
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Jumpers
X-Ref Target - Figure A-1
Figure A-1: ZC706 Jumper Header Locations
UG954_aA_01_042415
34
33
11
24
25
23
4
13
32
7 1
8
31
9 30
10
15
12
14 5
26 28
6
29
27
2
3
21
22
16
17
18
19
20
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Appendix B
VITA 57.1 FMC Connector Pinouts
Figure B-1 shows the pinout of the FPGA mezzanine card (FMC) low pin count (LPC) connector defined by the VITA 57.1 FMC specification. For a description of how the ZC706 evaluation board implements the FMC specification, see FPGA Mezzanine (FMC) Card Interface, page 67 and LPC Connector J5, page 71.
Figure B-2 shows the pinout of the FPGA mezzanine card (FMC) high pin count (HPC) connector defined by the VITA 57.1 FMC specification. For a description of how the ZC706 evaluation board implements the FMC specification, see FPGA Mezzanine (FMC) Card Interface, page 67 and HPC Connector J37, page 67.
X-Ref Target - Figure B-1
Figure B-1: FMC LPC Connector Pinout
VREF_A_M2C
PRSNT_M2C_L
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
GND
DP0_C2M_P
DP0_C2M_N
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GND
DP0_M2C_P
DP0_M2C_N
GND
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LA06_P
LA06_N
GND
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LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_L
GA1
3P3V
GND
3P3V
GND
3P3V
GND
CLK1_M2C_P
CLK1_M2C_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
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X-Ref Target - Figure B-2
Figure B-2: FMC HPC Connector Pinout
UG954_aB_02_100112
1
2
3
4
5
6
7
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VREF_B_M2C
GND
GND
CLK2_M2C_P
CLK2_M2C_N
GND
HA02_P
HA02_N
GND
HA06_P
HA06_N
GND
HA10_P
HA10_N
GND
HA17_P_CC
HA17_N_CC
GND
HA21_P
HA21_N
GND
HA23_P
HA23_N
GND
HB00_P_CC
HB00_N_CC
GND
HB06_P_CC
HB06_N_CC
GND
HB10_P
HB10_N
GND
HB14_P
HB14_N
GND
HB17_P_CC
HB17_N_CC
GND
VIO_B_M2C
GND
CLK3_M2C_P
CLK3_M2C_N
GND
GND
HA03_P
HA03_N
GND
HA07_P
HA07_N
GND
HA11_P
HA11_N
GND
HA14_P
HA14_N
GND
HA18_P
HA18_N
GND
HA22_P
HA22_N
GND
HB01_P
HB01_N
GND
HB07_P
HB07_N
GND
HB11_P
HB11_N
GND
HB15_P
HB15_N
GND
HB18_P
HB18_N
GND
VIO_B_M2C
GND
VREF_A_M2C
PRSNT_M2C_L
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
GND
DP1_M2C_P
DP1_M2C_N
GND
GND
DP2_M2C_P
DP2_M2C_N
GND
GND
DP3_M2C_P
DP3_M2C_N
GND
GND
DP4_M2C_P
DP4_M2C_N
GND
GND
DP5_M2C_P
DP5_M2C_N
GND
GND
DP1_C2M_P
DP1_C2M_N
GND
GND
DP2_C2M_P
DP2_C2M_N
GND
GND
DP3_C2M_P
DP3_C2M_N
GND
GND
DP4_C2M_P
DP4_C2M_N
GND
GND
DP5_C2M_P
DP5_C2M_N
GND
RES1
GND
GND
DP9_M2C_P
DP9_M2C_N
GND
GND
DP8_M2C_P
DP8_M2C_N
GND
GND
DP7_M2C_P
DP7_M2C_N
GND
GND
DP6_M2C_P
DP6_M2C_N
GND
GND
GBTCLK1_M2C_P
GBTCLK1_M2C_N
GND
GND
DP9_C2M_P
DP9_C2M_N
GND
GND
DP8_C2M_P
DP8_C2M_N
GND
GND
DP7_C2M_P
DP7_C2M_N
GND
GND
DP6_C2M_P
DP6_C2M_N
GND
GND
RES0
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_L
GA1
3P3V
GND
3P3V
GND
3P3V
GND
HA01_P_CC
HA01_N_CC
GND
GND
HA05_P
HA05_N
GND
HA09_P
HA09_N
GND
HA13_P
HA13_N
GND
HA16_P
HA16_N
GND
HA20_P
HA20_N
GND
HB03_P
HB03_N
GND
HB05_P
HB05_N
GND
HB09_P
HB09_N
GND
HB13_P
HB13_N
GND
HB19_P
HB19_N
GND
HB21_P
HB21_N
GND
VADJ
GND
PG_M2C
GND
GND
HA00_P_CC
HA00_N_CC
GND
HA04_P
HA04_N
GND
HA08_P
HA08_N
GND
HA12_P
HA12_N
GND
HA15_P
HA15_N
GND
HA19_P
HA19_N
GND
HB02_P
HB02_N
GND
HB04_P
HB04_N
GND
HB08_P
HB08_N
GND
HB12_P
HB12_N
GND
HB16_P
HB16_N
GND
HB20_P
HB20_N
GND
VADJ
GND
CLK1_M2C_P
CLK1_M2C_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
K
J
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G
F
E
D
C
B
A
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Appendix C
Xilinx Constraints File
The Xilinx Design Constraints (XDC) template for the ZC706 board provides for designs targeting the ZC706 evaluation board. Net names in the constraints correlate with net names on the latest ZC706 evaluation board schematic. Users must identify the appropriate pins and replace the net names with net names in the user RTL. See Vivado Design Suite User Guide: Using Constraints (UG903) for more information.
The FMC connectors J37 and J5 are connected to 2.5V V ADJ banks. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer.
Note: Refer to the Board Files area of the documentation tab on the Xilinx Zynq-7000 SoC ZC706 Evaluation Kit product page (www.xilinx.com/zc706) for the latest xdc constraints file.
Refer to the Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record concerning the CE requirements for the PC Test Environment:
Zynq-7000 SoC ZC706 Master Answer Record 51899
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Appendix D
Board Setup
Installing the ZC706 Board in a PC Chassis
Installation of the ZC706 board inside a computer chassis is required when developing or testing PCI Express® functionality.
When the ZC706 board is used inside a computer chassis (that is, plugged in to the PCIe® slot), power is provided from the ATX power supply 4-pin peripheral connector through the ATX adapter cable shown in Figure D-1 to J22 on the ZC706 board. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number
AZCBL-WH-1109-RA4. For information on ordering this cable, see [Ref 37].
To install the ZC706 board in a PC chassis:
1.
On the ZC706 board, remove all six rubber feet and standoffs and the PCIe bracket. The standoffs and feet are affixed to the board by screws on the top side of the board.
Remove all six screws.
2.
Re-attach the PCIe bracket to the ZC706 board using two of the previously removed screws.
3.
Power down the host computer and remove the power cord from the PC.
4.
Open the PC chassis following the instructions provided with the PC.
5.
Select a vacant PCIe expansion slot and remove the expansion cover (at the back of the chassis) by removing the screws on the top and bottom of the cover.
6.
Plug the ZC706 board into the PCIe connector at this slot and secure its PCIe bracket to the chassis with a screw at the top of the bracket.
X-Ref Target - Figure D-1
Figure D-1: ATX Power Supply Adapter Cable
UG954_aD_01_100212
To ATX 4-Pin Peripheral Power Connector
To J22 on ZC706 Board
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Installing the ZC706 Board in a PC Chassis
7.
The ZC706 board is taller than standard PCIe cards. Ensure that the height of the card is free of obstructions.
8.
Connect the ATX power supply to the ZC706 board using the ATX power supply adapter cable as shown in Figure D-1:
a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J22 on the ZC706 board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-pin adapter cable connector.
9.
Slide the ZC706 board power switch SW1 to the ON position. The PC can now be powered on.
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Appendix E
Board Specifications
Dimensions
Height 5.5 inch (14.0 cm)
Length 10.5 inch (26.7 cm)
Note: The ZC706 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI Express card.
Environmental
Temperature
Operating: 0°C to +45°C
Storage: –25°C to +60°C
Humidity
10% to 90% non-condensing
Operating Voltage
+12 V DC
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Appendix F
Regulatory and Compliance Information
Overview
This product is designed and tested to conform to the European Union directives and standards described in this section.
Refer to the Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record concerning the CE requirements for the PC Test Environment:
Zynq-7000 SoC ZC706 Master Answer Record 51899
Declaration of Conformity
The Zynq-7000 SoC ZC706 Evaluation Kit CE Declaration of Conformity is online.
CE Directives
2006/95/EC, Low Voltage Directive (LVD)
2004/108/EC, Electromagnetic Compatibility (EMC) Directive
CE Standards
EN standards are maintained by the European Committee for Electrotechnical Standardization (CENELEC). IEC standards are maintained by the International Electrotechnical Commission (IEC).
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Markings
Electromagnetic Compatibility
EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics – Limits and Methods of Measurement
EN 55024:2010, Information Technology Equipment Immunity Characteristics – Limits and Methods of Measurement
This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.
Safety
IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General requirements
EN 60950-1:2006, Information technology equipment – Safety, Part 1: General requirements
Markings
In August of 2005, the European Union (EU) implemented the EU WEEE Directive 2002/96/EC and later the WEEE Recast Directive 2012/19/EU requiring Producers of electronic and electrical equipment (EEE) to manage and finance the collection, reuse, recycling and to appropriately treat WEEE that the Producer places on the EU market after August 13, 2005. The goal of this directive is to minimize the volume of electrical and electronic waste disposal and to encourage re-use and recycling at the end of life.
Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life.
If you have purchased Xilinx-branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life, please do not dispose of them with your other household or municipal waste. Xilinx has labeled its branded electronic products with the WEEE Symbol to alert our customers that products bearing this label should not be disposed of in a landfill or with municipal or household waste in the EU.
This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment.
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Markings
This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive.
In August of 2005, the European Union (EU) implemented the EU WEEE Directive 2002/96/EC and later the WEEE Recast Directive 2012/19/EU requiring Producers of electronic and electrical equipment (EEE) to manage and finance the collection, reuse, recycling and to appropriately treat WEEE that the Producer places on the EU market after August 13, 2005. The goal of this directive is to minimize the volume of electrical and electronic waste disposal and to encourage re-use and recycling at the end of life.
Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life.
If you have purchased Xilinx-branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life, please do not dispose of them with your other household or municipal waste. Xilinx has labeled its branded electronic products with the WEEE Symbol to alert our customers that products bearing this label should not be disposed of in a landfill or with municipal or household waste in the EU.
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Appendix G
Additional Resources
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website.
For continual updates, add the Answer Record to your myAlerts.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.
References
The most up to date information related to the ZC706 board, its documentation, and schematics, are available on the following websites.
The Xilinx Zynq-7000 SoC ZC706 Evaluation Kit product page:
www.xilinx.com/zc706
The Zynq-7000 SoC ZC706 Evaluation Kit - Known Issues and Release Notes Master Answer Record is Zynq-7000 SoC ZC706 Master Answer Record 51899.
These Xilinx documents provide supplemental material useful with this guide:
1.
Zynq-7000 SoC Overview (DS190)
2.
Zynq-7000 SoC (Z-7030, 035, 045, and Z-7100): DC and AC Switching Characteristics
(DS191)
3.
LogiCORE IP DisplayPort Product Guide for Vivado Design Suite (PG064)
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References
4.
LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051)
5.
7 Series FPGAs Memory Resources User Guide (UG473)
6.
7 Series FPGAs Configuration User Guide (UG470)
7.
7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
8.
7 Series FPGAs Integrated Block for PCI Express Product Guide for Vivado Design Suite
(PG054)
9.
7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)
10.
Zynq-7000 SoC Technical Reference Manual (UG585)
11.
7 Series FPGAs Memory Interface Solutions User Guide (UG586)
12.
Zynq-7000 SoC Packaging and Pinout Product Specification (UG865)
13.
AMS101 Evaluation Card User Guide (UG886)
14.
Vivado Design Suite User Guide: Using Constraints (UG903)
15.
Zynq-7000 SoC PCB Design and Pin Planning Guide (UG933)
16.
Answer Record AR#61712
Other documents associated with Xilinx devices, design tools, intellectual property, boards, and kits are available at the Xilinx documentation website at:
www.xilinx.com/support/documentation/index
Documents associated with other devices used by the ZC706 evaluation board are available at these vendor websites:
17. Spansion Inc.: www.spansion.com (S25FL128SAGMFIR01)
18. Standard Microsystems Corporation: www.smsc.com/ (USB3320)
19. SanDisk: www.sandisk.com
20. SD Association: www.sdcard.org.
21. SiTime: www.sitime.com ( SiT9102 )
22. Silicon Labs: www.silabs.com ( Si570, Si5324C )
23. PCI Express® standard: www.pcisig.com/specifications
24. SFF-8431 specification: ftp.seagate.com/sff
25. Marvell Semiconductor: www.marvell.com, www.marvell.com/transceivers/alaska-gbe Send Feedback
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References
26. Analog Devices: www.analog.com/en/index.html (ADP 123, ADV7511KSTZ-P)
27. Texas Instruments: www.ti.com, www.ti.com/fusiondocs (UCD90120A, LMZ31506, LMZ31520, LMZ31710, LMZ31704, TPS54291PWP, TPS51200DR, PCA9548, TCA641APWR, TXS0108E)
28. Texas Instruments: www.ti.com/xilinx_usb (to order EVM USB-TO-GPIO)
29. Texas Instruments: www.ti.com/fusion-gui (to download FUSION_DIGITAL_POWER_DESIGNER)
30.
RTC-8564JE/NB Application Manual:
www.epsondevice.com/docs/qd/en/DownloadServlet?id=ID000498
31. Epson Electronics America: www.eea.epson.com. (RTC-8564JE)
32. Samtec: www.samtec.com. (SEAF series connectors)
33. Texas Instruments digital power: www.ti.com/ww/en/analog/digital-power/index.html
34. Maxim Integrated: www.maximintegrated.com (Maxim MAX13035E)
35. Micron Technology: www.micron.com (MT8JTF12864HZ-1G6G1, MT41J256M8HX-15E)
36. Digilent: www.digilentinc.com (Pmod Peripheral Modules)
37. Sourcegate Technologies: www.sourcegate.net. To order the custom Sourcegate cable, contact Sourcegate at, +65 6483 2878 for price and availability.
Note: The Xilinx ATX cable part number 2600304 is manufactured by Sourcegate Technologies and is equivalent to the Sourcegate Technologies part number AZCBL-WH-11009. Sourcegate only manufactures the latest revision. This is a custom cable and cannot be ordered from the Sourcegate website.
38. VITA FMC Marketing Alliance: www.vita.com (FPGA Mezzanine Card (FMC) VITA 57.1 specification)
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