JZ8PE255E
8-bit OTP
microcontroller
User data sheet
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JZ8PE255E
User
Manual
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V1.0 |
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V1.1 |
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V1.2 |
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Note Item:
When switching the TC0CON register Bit.3 (PAB) pre-divider selection bit and Bit.2~0 (TC0PSR2~PSR0) divider selection position, you need to turn off the watchdog enable first, and then turn on the watchdog enable after the switchover is completed, otherwise it is easy to cause reset.
When using the PWM function and the oscillator frequency multiplication function at the same time, it must be used with the PWM divider to avoid abnormal PWM function.
The factory default data for EEPROM is 0xA5;
Declaration:
The content of this material will be updated without notice as the product improves. Please consult our sales staff before using this material to ensure that the content of this material is the latest version.
Please use this product within the limits described in this document, and we will not be liable for any damage caused by improper use.
Although we are committed to improving the quality and reliability of our products, there is a certain probability that semiconductor products will malfunction or malfunction, so we are advised to pay due attention to safety during use to prevent personal injury or property damage caused by such accidents.
When exporting this product or this material overseas, you shall comply with applicable import and export control laws and regulations.
Reproduction or reproduction of part or all of the contents of this material in any form without the permission of the Company is strictly prohibited.
The test data of this data is for reference only, and the actual data is subject to the target prototype test.
Table of Contents
RPAGE~R0/IAR (Indirect Addressing Registers)11
RPAGE~R1/TC0C (TC0 Counting Register) 11
RPAGE~R2/PCL (PC Low Address Register) 11
RPAGE~R4/RSR (RAM Address Selection Register) 13
RPAGE~R6/P6 (P6 data register) 13
RPAGE~R8/TC1CON (TC1 control register) 14
RPAGE~R9/TC1PRD (TC1 Periodic Register) 14
RPAGE~RA/PWM1DT (PWM1 duty cycle register) 15
RPAGE~RB/PWM2DT (PWM2 duty cycle register) 15
RPAGE~RC/PWM3DT (PWM3 duty cycle register) 15
RPAGE~RD/P6IWE (P6 input mutation interrupt, wake up enable register.))15
RPAGE~RE/CPUCON (CPU Mode Control Register) 16
RPAGE~RF/INTF (Interrupt Beacon Register)17
RPAGE~R72/P6PH (P6 pull-up control register) 17
RPAGE~R73/P6PD (P6 pull-down control register) 17
RPAGE~R76/P6CON (P6 directional control register) 18
RPAGE~R78/E2PADR (E2P address register) 18
RPAGE~R79/E2PDAT(E2P Write Data Register)18
RPAGE~R7A/E2PCON(E2P control register)18
RPAGE~R7B/E2PREAD (E2P reading register) 19
RPAGE~R7D/TC0CON (control register) 19
RPAGE~R7E/SYSCON (System Control Register) 20
RPAGE~R7F/INTE (Interrupt Enable Register) 21
Interruption of on-site protection23
Overview of the reset function 24
The relationship between the operating frequency and LVR low-voltage detection26
External Crystal/Ceramic Oscillator 31
The clock module should be stated with 32
Figure 33 of the GPIO internal structure
Port-like metamorphosis awakens 34
TC0 Timing Calculation Statement 37
TC1 Timing Setting Description 38
TC1 Timing Calculation Statement 38
TC1 Idle Mode Wake Up Description 39
PWM internal structure with timing 40
PWM Pulse Width Modulation Setup Description 42
DC electric characteristics 48
Characteristic curved line diagram 49
Internal low-speed RC oscillator - pressure frequency characteristic curve 49
Internal low-speed RC oscillator - Temperature Frequency Characteristic Curve 49
Inner 910KHzRC oscillator - pressure frequency special curve 50
Inner 910KHzRC oscillator - temperature frequency special curve 50
Internal 8MHzRC oscillator - voltage characteristic curve 51
Internal 8MHzRC oscillator - temperature frequency characteristic curved line 51
Introduction to chips
Features
CPU configuration
2K×14-Bit OTP ROM
80×8-Bit SRAM
64×8-Bit EEPROM
(More than 10,000 times of erasure, the factory data is 0xA5).
8 levels of stack space
8-stage Programmable Voltage Reset (LVR) 1.2V, 1.6V, 1.8V, 2.4V
2.7V，3.1V，3.4V，3.7V
Operating current is less than 2 mA (4MHz/5V).
The working current is less than 5 A (14KHz/5V).
The sleep current is less than 1 A (sleep mode).
I/O configuration
1 set of 6 GPIO ports:P 6<5:0>
6 programmable pull-up I/O pins
6 programmable pull-down I/O pins
6 programmable wake-up ports:P 6<5:0>
6 Configurable Driver Enhancements P6<5: 0>
3 Configurable Secondary Sink Current Enhancement P6<2:0>
External interrupt :P 60
Work voltage
Operating voltage range: VLVR3.9V～
5.5V| Fcpu=0～8MHz VLVR2.4V～
5.5V| Fcpu=0～4MHz VLVR1.8V～
5.5V| Fcpu=0～1MHz
Working temperature
Operating temperature range:
-40℃-85℃
JZ8PE255E User Manual
Work frequency range
External crystal oscillator HXT, LXT
External crystal oscillator with built-in capacitor Disable, 7PF, 9PF, 12.5PF
Built-in IHRC oscillation circuit: 8MHz/1MHz/910KHz
Command Clock Divider Selection:
2Clock、4Clock、8Clock、 16Clock、32Clock
Built-in ILRC oscillation circuit: 14KHz(5V)/8KHz(3V).
Outer enclosing module
8Bit real-time clock/counter
3-way co-cycle 8Bit PWM
Interrupted sources
External outages
TC0 overflow interrupt
TC1 overflow/PWM periodic overflow interrupt
The E2P write is interrupted
The port status changes and is interrupted
characteristic
Four working modes
Programmable WDT timer
RTC clock count
OTP can do 1K programming twice
Packing type
JZ8PE255E- DIP/SOP8
JZ8PE255E- SOT23-6
Pin Assignment
VDD
GND
(SCL)/OSCI/P65
OSCO/P64
(VPP)/R ST / P6 3
P 60 / E X INT/PWM3/(SDA2)
P61/PWM2
P 62 / P W M 1 / TC0/(SDA1)
JZ8PE255E-8PIN pin bitmap
(SDA2)/EXINT/PWM3/P60 P62/PWM1/TC0/(SDA1)
GND
(SCL)/OSCI/P65
VDD
P63/RST/(VPP)
JZ8PE255E-6PIN pin bitmap
Pin description
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P60 | P60 | I/O |
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EXINT | I |
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PWM3 | O |
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SDA2 | I |
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P61 | P61 | I/O |
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PWM2 | O |
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P62 | P62 | I/O |
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PWM1 | O |
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TC0 | I |
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SDA1 | I |
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P63 | P63 | I/O |
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RST | I |
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VPP | I |
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P64 | P64 | I/O |
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OSCO | O |
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P65 | P65 | I/O |
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OSCI | I |
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SCL | I |
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VDD | -- |
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VSS | -- | 地 |
System block diagram
System block diagram
Memory structure
Program storage area
Diagram of the program store structure
Data storage area
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0x00 |
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0x01 |
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0x02 |
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0x03 |
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0x04 |
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0x05 |
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0x06 |
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0x07 |
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0x08 |
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0x09 |
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0x0A |
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0x0B |
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0x0C |
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0x0D |
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0x0E |
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0x0F |
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0x70 |
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0x71 |
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0x72 |
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0x73 |
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0x74 |
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0x75 |
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0x76 |
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0x77 |
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0x78 |
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0x79 |
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0x7A |
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0x7B |
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0x7C |
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0x7D |
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0x7E |
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0x7F |
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Description of the function
Manipulation registers
RPAGE~R0/IAR (Indirect Addressing Register).
00H(R) |
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IAR | RIND<7:0> |
| R |
| X |
The indirect addressing register is not an actual register, its main function is to serve as a pointer to indirect addressing. Any instruction that uses R0 as a pointer will actually correspond to the data that R4 (RAM address selection register) is pointing to by the lower 6 bits of RSR<5:0>.
RPAGE~R1/TC0C (TC0 counting register).
01H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
TC0C(R) | TC0C<7> | TC0C<6> | TC0C<5> | TC0C<4> | TC0C<3> | TC0C<2> | TC0C<1> | TC0C<0> |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TC0 is an 8-bit upstream counter with a selectable internal clock/external clock for the clock source, an interrupt for count overflow, and a read-to-write TC0C.
TC0 can be triggered by a signal edge on the P62 pin or an internal instruction cycle to generate a plus 1 operation (CONT. 4-bit definition). If the PAB bit (CONT.3) is cleared, a prescaler is assigned to TC0, and when a value is written to the TC0C register, the value of the prescaler is cleared 0。
RPAGE~R2/PCL (PC low address register).
02H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
PCL | PC<7> | PC<6> | PC<5> | PC<4> | PC<3> | PC<2> | PC<1> | PC<0> |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
A program counter (PC) is a pointer used to record the instructions to be processed by the CPU during each instruction cycle. During the CPU run cycle, the PC pushes the instruction pointer into program memory, and then the pointer increments by 1 to move on to the next cycle. JZ8PE255E has an 11-bit wide program counter (PC) with low bytes coming from the readable and writable PCL and high bits (PC<10:8>) being unreadable.
A stack is a pointer to the instructions returned by a recording program. When a subroutine is invoked, the PC presses the instruction pointer to the stack. When the return instruction is executed, the stack sends the instruction pointer back to the PC to continue the original process. JZ8PE255E has an 8-level stack that takes up neither program or data storage, and the stack pointer cannot be read or written.
Both the register PC and the built-in 8-level stack are 11 bits wide and are used for addressing 2K×14BitROM, JZ8PE255E programsStore mapping.
In general, the PC increases by one; On reset, all bits of the PC are zeroed.
The "JMP" directive allows direct loading of addresses as low as 11 bits, so JMP commands can jump anywhere on the current page (within the 2K range). The command "JMP" directly loads the lower 11 digits and presses PC+1 to the stack, so that the subroutine entry address can be accurately located as long as it is on the same page.
The top of the stack data is sent to the PC when the "RET" command is executed.
Any instruction to override the PCL value will affect the PC up to three digits accordingly. As a result, the resulting jumps can be extended to the 2K range.
When an interrupt occurs, the value of the program counter changes, and the PC assigns a value of 0x08.
The stack works like a buffer loop, which means that after 8 times of stacking , the data entering the stack will be overwritten on the 9th cycle
The data from the first stack is covered , and the data from the 10th stack will overwrite the data from the second stack, and so on.
RPAGE~R3/STATUS
03H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
STATUS | RST | GB1 | GB0 | T | P | Z | DC | C |
| R | R/W | R/W | R | R | R/W | R/W | R/W |
| 0 | 0 | 0 | 1 | 1 | X | X | X |
Bit<7>: RST-reset type flag 0: Other reset type
1: If the sleep mode is woken up by a pin state change Bit<6>: GB1 - undefined, universal read and write bits
Bit<5>: GB0 - undefined, generic read and write bits
Bit<4>: T-Time overflow bit
0: WDT overflow
1: Execute the "SLEEP" and "CWDT" commands or reset the low-voltage Bit<3>:P-power-down mark
0: Execute the SLEEP command
1: Power-on reset or execution of "CWDT" command affects the events of T/P as shown in the following table:
| RST | T | P |
| 0 | 1 | 1 |
| 0 |
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| 0 | 1 | 0 |
| 0 | 0 |
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| 0 | 0 | 0 |
| 1 | 1 | 0 |
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| 1 | 1 |
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| 1 | 0 |
Bit<2>: Z-zero flag is set when the arithmetic or logical operation result is zero”1” 0:
When arithmetic or logical operations result is not 0
1: When the arithmetic or logical result is 0 Bit<1>: DC-Assisted Carry flag
0: When the addition operation is executed, the lower four digits are not carried; / When subtracting is performed, the lower four bits generate a debit
1: When performing addition operations, the lower four digits are generated by carrying; When the /subtraction operation is performed, the lower four bits do not produce a debit bit<0>:C-carry flag
0: When the addition operation is executed, the upper four digits are not carried; When / subtraction operations are performed, the upper four bits generate a borrow
1: When performing addition operations, the upper four digits are generated by carrying; / When subtracting is performed, the upper four digits do not produce a debit
RPAGE~R4/RSR (RAM Address Selection Register).
04H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
RSR | - | RSR<6> | RSR<5> | RSR<4> | RSR<3> | RSR<2> | RSR<1> | RSR<0> |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 1 | X | X | X | X | X | X | X |
RSR<6: 0> is used to select the RAM register address (addressing range: 0x10~0x5F) in the indirect addressing mode
RSR is used with R0 for indirect addressing operations. The user can put the address corresponding to a register into the RSR, and then access the indirect addressing register R0, which will point to the register of the corresponding address in the RSR.
RPAGE~R6/P6 (P6 data register).
06H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
P6 | - | - | P65 | P64 | P63 | P62 | P61 | P60 |
| R | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
Port data registers, P6 port is 6 bits
RPAGE~R8/TC1CON (TC1 control register).
08H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 Bit1 Bit0 | ||
TC1CON | TC1EN | PWM3EN | PWM2EN | PWM1EN | TC1PTEN |
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| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7>: TC1EN - TC1/PWM Counter Enable Control 1: Enable
0: Forbidden
If the TC1PRD register is set, the TC1 count is reset to the TC1PRD preset value, and the TC1 counts from 1. Bit<6:4>:PWM3EN~PWM1EN - PWM3~PWM1 enable bits
1: Enable (PWM3 (P60), PWM2 (P61), PWM1 (P62), the corresponding port is set as output).
0: Forbidden
Bit<3>:TC1PTEN -TC1
The pre-crossover selects the control bits
Bit<2:0>:TC1PSR2~TC1PSR1
Crossover coefficient selection bits:
TC1PTEN | TC1PSR<2> | TC1PSR<1> | TC1PSR<0> |
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0 | 0 | 0 | 0 | 1:1 |
1 | 0 | 0 | 0 | 1:2 |
1 | 0 | 0 | 1 | 1:4 |
1 | 0 | 1 | 0 | 1:8 |
1 | 0 | 1 | 1 | 1:16 |
1 | 1 | 0 | 0 | 1:32 |
1 | 1 | 0 | 1 | 1:64 |
1 | 1 | 1 | 0 | 1:128 |
1 | 1 | 1 | 1 | 1:256 |
RPAGE~R9/TC1PRD (TC1 Cycle Register).
09H(R) |
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TC1PRD | TC1PRD<7:0> | |||||||
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7:0>:TC1PRD<7:0>-PWM period 8-bit data
RPAGE~RA/PWM1DT (PWM1 duty cycle register).
0AH(R) |
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PWM1DT | PWM1DT<7:0> | |||||||
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7:0>:PWM1DT <7:0>-PWM1 duty cycle 8-bit data
RPAGE~RB/PWM2DT (PWM2 duty cycle register).
0BH(R) |
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PWM2DT | PWM2DT<7:0> | |||||||
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7:0>:PWM2DT<7:0>-PWM2 Duty Cycle 8-bit data
RPAGE~RC/PWM3DT (PWM3 duty cycle register).
0CH(R) |
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PWM3DT | PWM3DT<7:0> | |||||||
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7:0>:PWM3DT<7:0>-PWM3 duty cycle 8-bit data
RPAGE~RD/P6IWE (P6 input change interrupt, wake-up enable register).
0DH(R) | Bit7 | Bit6 |
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P6IWE | - | - | P6IWE<5:0> | |||||
| R | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<5:0>:P6IWE<5:0>- P6 Input Change, Interrupt, Wake, Enable Control Bit 1: Enable
0: Forbidden
RPAGE~RE/CPUCON (CPU MODE CONTROL REGISTER).
0EH(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
CPUCON | CRYCAP<1> | CRYCAP<0> | TC0CKS | TC1CKS | IPWM1EN | STPHX | CLKMD | IDLE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| X | X | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7:6>:CRYCAP<1:0>-crystal oscillator capacitor selection bit
CRYCAP<1> | CRYCAP<0> |
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0 | 0 |
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0 | 1 |
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1 | 0 |
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1 | 1 |
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Bit<5>: TC0CKS-TC0 Clock Source Selection Bit 1: Select System Clock/Low Speed Clock
0: Select the instruction cycle clock/external input clock Bit<4>:TC1CKS-TC1/PWM
Clock source selection bits
1: Select the system clock
0: Select the instruction cycle clock Bit<3>: IPWM1EN-PWM1 dead-time complementary output enable bit
1: Enables dead-band complementary output (PWM1-P62/IPWM1-P61).
0: Disable dead time complementary output Bit<2>: STPHX - high-speed clock control bit
1: Stop high-speed clocks, including IRC and crystal oscillator clocks (excluding RTC clocks).
0: The high-speed clock is working normally Bit<1>: CLKMD - System clock selection bit
1: The system clock uses a low-speed RC oscillator clock
0: The system clock uses a high-speed IRC or crystal oscillator clock
When the system enters the low-speed mode from high-speed mode, set CLKMD=1 and then set STPHX=1, and when the system enters high-speed mode from low-speed mode, set STPHX=0 and then set CLKMD=0.
Bit<0>: IDLE-Idle mode selection bit
1: When the system executes the SLEEP command, it enters idle mode, and the system clock works normally
0: The system enters sleep mode when executing the SLEEP command
RPAGE~RF/INTF (Interrupt Flag Register).
0FH(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
INTF | - | - | - | E2PIF | TC1IF | EXIF | P6ICIF | TC0IF |
| R | R | R | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7: 5>: unused bits
Bit<4>: E2PIF-EEPROM write completion interrupt flag
Bit<3>:TC1IF-TC1
Timed overflows/PWM
Periodic overflow break flag
Bit<2>: EXIF - External Port Interrupt Flag
Bit<1>:P 6ICIF-P6
Port status change interrupt flag Bit<0>:TC0IF-TC0
Timing overflow break flags
1: There is an interruption, and the software clears 0
0: No interruption
Note: When clearing the interrupt marker, you must use MOVRF,A operation, and BTC cannot be used and ANDRF,A command operation.
RPAGE~R72/P6PH (P6 pull-up control register).
72H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
P6PH | - | - | P6PH<5> | P6PH<4> | P6PH<3> | P6PH<2> | P6PH<1> | P6PH<0> |
| R | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit<5:0>:P6PH<5:0>-P6 pull-up enabled
0: Enabled
1: Forbidden
RPAGE~R73/P6PD (P6 pull-down control register).
73H(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
P6PD | - | - | P6PD<5> | P6PD<4> | P6PD<3> | P6PD<2> | P6PD<1> | P6PD<0> |
| R | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit<5:0>:P6PD<5:0> pull-down enable control 0: enabled
1: Forbidden
RPAGE~R76/P6CON (P6 direction control register).
76H(R) | Bit7 | Bit6 |
| |||||
P6CON | - | - | P6CON<5:0> | |||||
| R | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit<5:0>:P6CON<5:0>- P6 directional control bit
1: Input
0: output
RPAGE~R78/E2PADR (E2P address register).
78H(R) | Bit7 | Bit6 |
| |||||
E2PADR | - | - | E2PADR<5:0> | |||||
| R | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<5:0>:E2PADR<5:0>- EEPROM 地址位
RPAGE~R79/E2PDAT (E2P Write Data Register).
79H(R) |
| |||||||
E2PDAT | E2PDAT<7:0> | |||||||
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7:0>:E2PDAT<7:0>-EEPROM write data bits
RPAGE~R7A/E2PCON (E2P Control Register).
7AH(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
E2PCON | WRERR | PC<10> | PC<9> | PC<8> | - | CS | E2PRDEN | E2PWREN |
| R/W | R | R | R | R | R/W | R/W | R/W |
| 0 | X | X | X | 0 | 0 | 0 | 0 |
Bit<7>: WRERR-EEPROM Write Failure Flag 1: Failed to write data
0: The write function is normal/not written
Bit<2>: CS-EEPROM enable bit
1: Enable the EEPROM module function
0:
forbid EEPROM
Module features Bit<1>:E2PRDEN-EEPROM
Read data enable bit
1: Enable (After enabling the EEPROM read state, you need to wait for 2us to start reading E2PREAD register data).
0: Forbidden
Bit<0>: E2PWREN-EEPROM write data enable bit
1: Enable (0 automatically after EEPROM write completion).
0: Forbidden
RPAGE~R7B/E2PREAD (E2P Read Data Register).
7BH(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
E2PREAD |
| |||||||
| R | R | R | R | R | R | R | R |
| X | X | X | X | X | X | X | X |
Bit<7:0>:E2PREAD<7:0>-EEPROM read bits
RPAGE~R7D/TC0CON (control register).
7D(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 Bit1 Bit0 | ||
TC0CON | TC0EN | RTCS | TS | TE | PAB | TC0PSR<2:0> | ||
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
Bit<7>: TC0EN-TC0 Count enable flag bit 0: forbid
1: Enable
Bit<6>: RTCS-RTC clock selection bit
0: Prohibition of RTC clocks (crystal oscillator clocks).
1:
Enable
CTS
clock
(TC0
The clock source is a crystal oscillator clock） Bit<5>:TS-TC0
Source selection bits
0: internal instruction cycle clock (TC0CKS=0)/system clock (TC0CKS=1).
1: External Input Clock (TC0CKS=0)/Low Speed Oscillator Clock (TC0CKS=1) Bit<4>: TE-TC0 signal edge selection bit
0: The TC0 pin signal changes from low to high plus 1
1: The TC0 pin signal changes from high to low plus 1
Bit<3>: PAB-Prescaler Allocation Bit 0: Prescaler Allocation to TC0
1: The prescaler is distributed to the WDT
Bit<2:0>:TC0PSR2~TC0PSR0-TC0/WDT Pre-crossover selection control bit:
TC0PSR<2> | TC0PSR<1> | TC0PSR<0> |
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0 | 0 | 0 | 1:2 | 1:1 |
0 | 0 | 1 | 1:4 | 1:2 |
0 | 1 | 0 | 1:8 | 1:4 |
0 | 1 | 1 | 1:16 | 1:8 |
1 | 0 | 0 | 1:32 | 1:16 |
1 | 0 | 1 | 1:64 | 1:32 |
1 | 1 | 0 | 1:128 | 1:64 |
1 | 1 | 1 | 1:256 | 1:128 |
RPAGE~R7E/SYSCON (System Control Registers).
7E(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
SYSCON | WDTEN | EIS | PEDGEN | NEDGEN | TC0WE | TC1WE | E2PWE | EXINTWE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7>: WDTEN-WDT enable control 1: enabled
0: Forbidden
Note: WDTEN is required to enable the watchdog and enable is selected for the OPTION option Watchdog. Bit<6>: EIS-P60 pin external interrupt enable bit
1: Enable the P60 external interrupt function, the P60 pin is set to the input port by default, and the pin status can be read by the P6 port
0: Forbidden, P60 为
GPIO,EXINT
The channel is shielded
Bit<5>:P EDGEN - External interrupt rising edge triggers the selection bit
1: Enable
0: Forbidden
Bit<4>: NEDGEN - External interrupt falling edge triggers selection bit 1: enabled
0: Forbidden
Bit<3>: TC0WE-TC0 wake-up enable bit
1: Enable TC0 wake-up, wake up in idle mode, wake up sleep in RTC mode, and wake up in idle mode
0: TC0 is not allowed to wake up
In RTC mode, set TC0WE=1&RTCS=1 to hibernate when LXT continues to work and will not stop, otherwise sleep will stop LXT. Bit<2>: TC1WE-TC1/PWM wake-up enable bit
1: Enables TC1/PWM wake-up, which can wake up the idle mode
0:
forbid TC1/PWM
awaken Bit<1>:E2PWE-EEPROM
Write the wake up enable bit
1: Enable (write failure will still wake up, pay attention to check the write failure flag).
0: Forbidden
Bit<0>: EXINTWE-External interrupt wake-up enable bit 1: enabled
0: Forbidden
RPAGE~R7F/INTE (interrupt enable register).
7F(R) | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
INTE | - | - | - | E2PIE | TC1IE | EXIE | P6ICIE | TC0IE |
| R | R | R | R/W | R/W | R/W | R/W | R/W |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit<7: 5>: unused bits
Bit<4>:E2PIE-EEPROM
Write completion interrupt enable bit Bit<3>:TC1IE-TC1
Timed overflows/PWM
Periodic overflow interrupts the enable bit
Bit<2>: EXIE - External port interrupt enable bit
Bit<1>:P 6ICIE-P6
Interrupt enable bit for port status change Bit<0>:TC0IE-TC0
Timing overflow interrupts the enable bit
1: Enable
0: Forbidden
Interrupt
JZ8PE255E has 5 interrupt sources, and no matter which interrupt is used, the total interrupt, or "EI" instruction, must be enabled. The interrupt vector is a fixed default address of 008H. Here are the characteristics of each interrupt:
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| EI + EXIE=1 | EXIF |
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| EI + P6ICIE=1 | P6ICIF |
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| EI + TC0IE=1 | TC0IF |
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| EI + TC1IE=1 | TC1IF |
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| EI + E2PIE=1 | E2PIF |
RPAGE's RF is an interrupt status flag register, which records the interrupt flag when an interrupt is requested when an interrupt is requested. R7F sets registers for interrupts, and allows and disallows interrupts are set in both registers. The total interrupt is allowed by placing an "EI" instruction, and conversely, the total interrupt is forbidden by placing a "DI" instruction. When an interrupt is generated, its next instruction execution will be executed from the interrupt vector address 008H. The corresponding interrupt flag must be cleared before leaving the interrupt service program in order to avoid interrupt malfunction.
Schematic diagram of the interrupt principle
Interrupt on-site protection
In the process of responding to interrupts, it is strongly recommended to use interrupt protection in the program, save the contents of ACC, R3, and R4 until you leave the interrupt subroutine, and then reload the saved values into ACC, R3, and R4, so as to avoid an error when the interrupt subroutine is executed, and there are instructions to change the values of ACC, R3, and R4, resulting in an error when returning to the main program. As shown in the figure below:
Schematic diagram of software outage site protection
reposition
Overview of the reset function
The JZ8PE255E system provides 4 reset modes:
POR power-on reset
The RESET pin input resets low
WDT watchdog overflow reset
LVR Low Voltage Reset
When any of these resets occur, all system registers are initialized to the reset value, the program stops running, and the program counter PC clears to zero. After the reset is complete, the system restarts from vector 0000H.
Any kind of reset situation requires a certain response time, and the system reset mechanism can ensure a reliable reset of the MCU. Different types of oscillators take different amounts of time to complete a reset. As a result, the rise speed of the VDD and the starting time of the different oscillators are not fixed. RC oscillators have the shortest starting time, while crystal oscillators have longer starting times. In the process of user terminal use, attention should be paid to the requirements of the application scenario for the power-on reset time.
WDT watchdog reset
Watchdog reset is a protective setting of the system. Under normal conditions, the program clears the watchdog timer to zero. If an error occurs, the system is in an unknown state, the watchdog timer overflows, and the system resets. After the watchdog is reset, the system reboots into a normal state.
Watchdog timer status: The system detects whether the watchdog timer is overflowing, and if it is overflowing, the system resets;
System Initialization: All system registers are set to initialization defaults;
The oscillator starts working: the oscillator starts providing the system clock;
Execute the program: the power-on is over, and the program starts to run; Watchdog Timer Application Note Item:
Before zeroing out the watchdog, checking the status of the I/O port and the contents of the RAM can enhance the reliability of the program.
The watchdog cannot be cleared during the interruption, otherwise the main program will not be detected.
There should only be one watchdog action in the main program, and this architecture can maximize the protection function of the watchdog.
POR power-on reset
Power-on reset is closely related to LVR operation. The power-up process of the system is in the form of a gradual upward curve, and it takes a certain amount of time to reach the normal level value.
Power-on: The system detects a rise in the power supply voltage and waits for it to stabilize;
External Reset (External Reset Pin Enable State Only): The system detects the external reset pin state. If it is not high, the system remains reset until the external reset pin is released;
System Initialization: All system registers are set to initial values;
The oscillator starts working: the oscillator starts providing the system clock;
Execute the program: the power-on is over, and the program starts to run;
The power-on reset time is determined by the Reset Time selection in OPTION, as shown in the following table
PWRT 与 WDT |
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PWRT=WDT |
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PWRT=WDT |
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PWRT=WDT |
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PWRT=WDT |
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PWRT≠WDT |
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LVR Low Voltage Reset
Power-down reset is a case of system voltage dip caused by external factors (e.g., disturbances or changes in external loads) that may cause the system to operate abnormally or to execute the program incorrectly.
Voltage dips can enter the system dead zone. A system dead zone means that the power supply does not meet the minimum operating voltage requirements of the system. The figure above is a typical power-down reset schematic. In the diagram, the VDD is severely disturbed and the voltage drops very low. The area above the dotted line works normally, and in the area below the dotted line, the system enters an unknown working state, and this area is called dead
District. When VDD drops to V1, the system is still in a normal state; When VDD drops to V2 and V3, the system enters a dead zone, which can easily lead to errors. The system can enter a dead zone in the following situations:
DC in use:
When the battery voltage is too low or the microcontroller drives the load, the system voltage may drop and enter the dead zone. At this point, the power supply does not drop further to the LVR sense voltage, so the system remains in a dead zone.
AC in use:
When the system is AC powered, the DC voltage value is affected by the noise in the AC power supply. When an external load is too high, such as when driving a motor, interference from load action also affects the DC power supply. If the VDD falls below the minimum operating voltage due to interference, the system may enter an unstable operating state. In AC applications, the system takes a long time to power on and off. Among them, the power-on sequencing protection makes the system power on normally, but the power-down process is similar to the situation in DC application, after the AC power supply is turned off, the VDD voltage is easy to enter the dead zone in the process of slowly dropping.
Operating frequency vs. LVR low voltage detection
In order to improve the performance of the system in power-down reset, it is first necessary to determine the minimum operating voltage value that the system has. The minimum working voltage of the system is related to the execution speed of the system, and the minimum working voltage value is different under different execution speeds.
As shown in the diagram above, the normal operating voltage area of the system is generally higher than the system reset voltage, and the reset voltage is determined by the low voltage detection (LVR) level. When the execution speed of the system increases, the minimum working voltage of the system also increases accordingly, but because the system reset voltage is fixed, there will be a voltage area between the minimum working voltage of the system and the system reset voltage, and the system cannot work normally and will not be reset, and this area is a dead zone.
In order to avoid dead voltages, the corresponding LVR reset voltage point should be selected when selecting the operating frequency . As shown in the table below:
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| 2 Clocks | LVR=3.1V |
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| 2 Clocks | LVR=2.4V |
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| 2 Clocks | LVR=1.8V |
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| 2 Clocks | LVR=1.8V |
Note: 1. Working frequency = instruction cycle frequency = IRC frequency + Clocks frequency division; 2. The corresponding value of this working frequency and LVR reset voltage point is only the recommended value, and the user can adjust the reset voltage point appropriately according to the specific application used in the process of use.
Working Mode
JZ8PE255E can operate in 4 operating modes with different clock frequencies. These modes can control the operation of the oscillator, the execution of the program, and the functional loss of the analog circuit.
High-speed mode: the system clock selects the high-speed IRC clock;
Low-speed mode: the system clock selects the internal low-speed clock;
Idle mode: the system clock works normally, and other parts enter sleep (TC0 and TC1/PWM select the system clock to continue working and wake up the system, RTC overflow and P6 port status changes can wake up the system);
Sleep mode: all functions are suspended, the system enters sleep (RTC mode can work), and can be woken up by P6 port status changes and RTC overflow wakeup;
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IHRC |
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ILRC |
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TC0 |
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TC1/PWM |
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| - | - | P6IC,TC0,TC1/PWM, | P6IC,RTC |
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High-speed mode
High-speedmodeisthesystemhigh-speedclockworkingmode,and thesystemclocksource is provided by the high-speed RC oscillator. The program is executed. After power-on reset or any reset trigger, the system enters high-speed mode to execute the program.
When the system is awakened from sleep mode, it enters high-speed mode. In high-speed mode,the high-speedoscillatorworksnormallyandthepowerconsumptionisthehighest.
The program is executed, and all functions are controllable;
The system rate is high-speed;
Both the high-speed oscillator and the internal low-speed oscillator work normally;
The CPU mode control registers allow the system to switch from high-speed mode to any other mode of operation;
The system wakes up from sleep mode and enters high-speed mode;
Low-speed mode can be switched to high-speed mode;
Enter from high-speed mode to idle mode, and return to high-speed mode after waking up;
Low speed mode
Low-speed mode is the low-speed clock operation mode of the system. The system clock source is provided by an internal low-speed RC oscillator. Low-speed mode is controlled by the CLKMD bit of the CPU mode control register . When CLKMD=0, the system is in high-speed mode; When CLKMD=1, the system enters low-speed mode. After entering low-speed mode, the high-speed oscillator cannot be automatically disabled, and must be disabled by the SPTHX bit to reduce power consumption.
The program is executed, and all functions are controllable;
The system rate is low;
The internal low-speed RC oscillator works normally, and the high-speed oscillator is controlled by STPHX=1. In low-speed mode, it is highly recommended to stop the high-speed oscillator;
The CPU mode control registers can be switched to other working modes in low-speed mode;
Enter sleep mode from low-speed mode and return to low-speed mode after waking up;
The high-speed mode can be switched to the low-speed mode;
Enter from low-speed mode to idle mode, and return to low-speed mode after waking up;
Idle mode
Idle mode is another ideal state. In sleep mode, all functions and hardware devices are disabled, but in idle mode, the system clock remains working, and the power consumption in idle mode is greater than that in sleep mode. In idle mode, the timer and PWM with wake-up function are still working normally, and the clock source of the timer and PWM is the system clock that is still working. In idle mode, there are 4 ways to wake up the system: 1. Triggered by the change of P6 port status; 2. TC0 timer wakes up; 3. TC1 timer/PWM cycle overflow can be woken up; 4. RTC wakes up at a regular interval. The user can set a fixed period for a given timer or PWM, and the system will be woken up when it overflows. THE CPU MODE CONTROL REGISTER IDLE BIT DETERMINES WHETHER TO ENTER IDLE MODE, AND WHEN IDLE=1, THE SYSTEM ENTERS IDLE MODE.
The program stops executing and all functions are disabled;
The timer with wake-up function works normally;
The oscillator as the system clock source works normally, and the working status of other oscillators depends on the configuration of the system working mode;
Enter from high-speed mode to idle mode, and return to high-speed mode after being woken up;
Enter from low-speed mode to idle mode, and return to low-speed mode after being woken up;
In idle mode, the wake-up mode is triggered by the state change of P6 port, TC0 timer overflow, TC1 timer overflow/PWM cycle overflow, and RTC timer wake-up.
The TC0 and TC1/PWM functions remain active in idle mode ;
Sleep mode
Sleep mode is the ideal state of the system, no programs are executed (except for RTC) and the oscillator also stops working. The power consumption of the entire chip is less than 1uA. Sleep mode can trigger wake-up, RTC overflow wake-up, triggered by P6 port state changes . If you enter sleep mode from high-speed mode or low-speed mode, you will return to the corresponding mode when you wake up. The CPU mode controls whether the IDLE bit of the register enters sleep mode, and when IDLE=0, the system enters sleep mode.
The program stops executing and all functions are disabled;
All oscillators, including external high-speed oscillators, internal high-speed oscillators, and internal low-speed oscillators, stop working;
Power consumption is less than 1uA;
Enter sleep mode from high-speed mode, and return to high-speed mode after being woken up;
Enter sleep mode from low-speed mode, and return to low-speed mode after being woken up;
The wake-up source of sleep mode is triggered by the state change of the P6 port and the RTC overflow wake-up.
System clock
JZ8PE255E There are 3 types of oscillators integrated inside . Please refer to the table below
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| 14KHz |
| 32.768K～400K |
| 400K～16M |
Internal RC oscillator
JZ8PE255E offers an internal RC mode with a frequency default of 8MHz.
The internal RC oscillation mode includes three frequency values: 8MHz, 1MHz, and 910KHz. The IRC operating frequency can be selected by setting the configuration bit of OPTION, and here is how they correspond
Firc |
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8 M |
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1 M |
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910K |
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JZ8PE255E PROVIDES A VARIETY OF CROSSOVER OPTIONS, WHICH CAN BE SELECTED IN THE OPTION, WHICH IS SUITABLE FOR MORE OCCASIONS. As shown in the table below:
Clocks |
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2clock |
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4clock |
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8clock |
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16clock |
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32clock |
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External crystal/ceramic oscillator
In most applications, pins OSCO and OSCI can be connected to a crystal or ceramic resonator to generate oscillations, and the circuit diagram is shown below, which is suitable for either HXT or LXT mode, C1 and C2 in the table recommended value. Due to the different characteristics of each resonator, the user should refer to its specifications to select the appropriate value of C1 and C2.
Crystal Oscillator Application Circuit Capacitance Selection Reference for Crystal Oscillator or Ceramic Oscillator:
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| C1(pF) | C2(pF) |
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| HXT | 455KHz | 100-200 | 100-200 | - |
| LXT | 32.768KHz | 5-40 | 5-40 | 12.5pf |
HXT | 1 MHz | 5-30 | 5-30 | 9pf | |
4 MHz | 5-30 | 5-30 | - |
Note: The above data is for reference only, and all data are subject to the actual test
Clock Module Application Notes
The internal oscillator is the most commonly used oscillation mode, which can eliminate the need for external circuitry;
When using an external clock input, the clock signal is to be input from the OSCI and OSCO can be floated;
The clock frequency of each oscillation mode may be slightly different due to different external conditions, so it should be reasonably selected according to the needs when using;
I/O ports
JZ8PE255E has 1 set of bidirectional I/O ports, a total of 6 inputs, 6 outputs, I/O can be reused for other functions. 6 Programmable Pull-Up I/O Pins: P6<5:0>;
6 Programmable Pull-Down I/O Pins: P6<5:0>;
6 Configurable Driver Enhancement I/O Pins: P6<5:0> Sink-Boost, P6<5:4>, P6<2:0>-Sink Boost;
3 configurable two-stage sink current enhancement :P 60, P61, P62;
6 Programmable Port State Change Wake I/O Pins :P 6<5:0>;
GPIO internal structure diagram
The following internal structure diagram is for reference only and does not represent the actual circuit.
IO control registers/data registers/pull-up/pull-down structure circuitry
Port drive capability description
JZ8PE255E has 6 first-stage sink current enhancement IO ports (P6<5:0>) and 5 first-stage source current enhancement IO ports(P6<5:4>, P6<2:0>), 3 secondary sink current enhancement IO ports (P60, P61, P62). The pull-sink current is enhanced by configuring OPTION
Select [Driver Enhancement] and [Secondary Driver Enhancement] in the options.
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| IOH 6mA IOL 16mA | P6<5:0> |
| IOH 12mA | P6<5:4>、P6<2:0> |
| IOL 21mA | P6<5:0> |
| IOL 27mA | P60,P61,P62 |
Note: The driving capacity is for reference only, and the specific values are mainly based on actual measurements.
Port Schmidt parameters
The table of Schmitt characteristics of the JZ8PE255E ports is as follows (for reference only):
| SMT |
P6<5:0> | 0.54*VDD/0.25*VDD |
The above parameters are for reference only, please refer to the measured data of the target prototype.
Wake up from a change in port status
JZ8PE255E Contains 6 programmable port state change wake-up I/O: P6<5:0>. The chip executes the "SLEEP" command to enter sleep mode. At this point, the system clock stops, all modules stop working, and WDT (if enabled) clears to 0, but continues to run. To wake up from a port state change, you can choose to continue the original process (DI before sleep) or execute the corresponding jump (EI before SLEEP) and turn on the corresponding enable control bit to jump to the interrupt subroutine.
The port status is changed to the query method to wake up the setting
1. The wake-up port of the P6 port is set as input;
2. Select the internal pull-up or pull-down of the wake-up port according to your needs;
4. Enable P6 input change to wake up enable register P6IWE;
5. Execute DI instructions without entering the interrupt address port;
6. Execute the "SLEEP" command to enter the SLEEP mode;
7. After waking up, execute the next command of SLEEP;
The port status is changed to interrupt the wake-up setting
1. The wake-up port of the P6 port is set as input;
2. Select the internal pull up and down of the wake-up port according to your needs;
3. Enable independent interrupt and wake-up control for port state change;
4. Enable the state change of port P6 to be interrupted.
5. Execute the "EI" command and wait to enter the interrupt address port;
6. COMMAND "SLEEP" TO ENTER SLEEP MODE;
7. After waking up, it will enter the interrupt address port, and after exiting the interrupt, execute the next SLEEP command;
timer
TC0 timing counter
JZ8PE255E provides an 8-bit counter as a prescaler for TC0 and WDT. The prescaler is only used by TC0 or WDT at the same time, and the PAB bit in the CONT register determines the allocation of the prescaler. TC0PSR<2: 0> three digits determine the precrossover ratio. In TC0 mode, each time TC0C is written to a value, the predivider register is cleared. When the prescaler is assigned to WDT mode, the values of the WDT and precrossover registers are zeroed out when the "CWDT" or "SLEEP" instructions are executed. If the prescaler is assigned to TC0 and then to WDT, the contents of the prescaler counter will be automatically cleared and vice versa.
TC0 is an 8Bit upstream counter that works as long as the clock is on. The clock source can be either an internal system clock (rising edge triggered), an external clock (input by the TC0 pin with selectable trigger edge), or an RTC mode selected to use an external crystal clock count. TC0 adds 1 to the counter each time the clock arrives. An 8Bit counter is provided as a prescaler for TC0. The TC0 predivider, trigger edge, clock, and more can be set via the CONT register .
TC0 count overflow can form an interrupt signal.
mode，TC0
The interrupt can wake up the circuit, and after waking up, you can choose to enter the interrupt or continue to execute the original program.
The method refers to Port State Change Wake.
Block diagram of the TC0/WDT
TC0 Timing Setting Instructions
Assign an initial value to the TC0C register;
set the value of the TC0CON register (select as timer or counter and precrossover);
For use as a counter, you need to select TC0 in the TC0CON register to add 1 to the positive or negative edge of the TC0 external signal
If you need to perform the interrupt function, you must set TC0IE(Bit0) in the R7F register to 1 and execute the EI instruction.
In the interrupt program part, ACC, STATUS and R4 will be manually saved in the stacker, and then taken out of the stack after the RETI command is executed, and the TC0 interrupt flag should be cleared before exiting the interrupt;
TC0 Timing Calculation Description
The TC0 timing function writes a value to the TC0 register, assigns an initial value to the given timer, and the timer starts to accumulate from the initial value position until the timer overflows and produces an interrupt.
TC0 Timing Time Calculation Formula (Optional Internal Command Period Clock):
TC0
Timed time =
System clock crossover
/Dark × (TC0
Frequency) × (256 − TC0
Initial value)
Example:
System clock division = 2clock, Fosc = 8 MHz, TC0 division selection = 4 division, TC0 initial value = 156;
TC0
Timed time = 2/8 × 4 × 256 − 156 = 100 us
TC0 Timing Time Calculation Formula (Optional External Input Clock):
TC0
Timed time =
External input clock × (TC0
Frequency) × (256 − TC0
Initial value)
Example:
External input clock = 1 MHz, TC0 divide selection = 4 division, TC0 initial value = 156;
TC0
Timed time = 1 × 4 × 256 − 156 = 400 us
TC1 timing counter
The TC1 timing counter provides an 8-bit prescaler, and the TC1PSR<2:0> three digits of the TC1CON register determine the precrossover ratio. In TC1 mode, the precrossover register is cleared every time TC1EN/PWM1EN/PWM2EN/PWM3EN is enabled.
TC1 is an 8Bit upstream counter. The TC1 timer needs to enable TC1EN to work, the clock source is the internal instruction clock/internal system clock, and the counter implementation is incremented by 1 for each clock cycle. If TC1IE and EI are enabled, the system will jump to the corresponding interrupt vector address and execute the interrupt service program. In IDLE mode, the TC1 interrupt can wake up the circuit (clock selects the system clock) and can select the forward interrupt after waking up
Or continue to run the original program, and wake up with the method referring to the port state change.
TC1 block diagram
TC1 Timing Setting Description
1. Assign an initial value to the TC1PRD register;
2. Set the TC1CON register and configure the pre-crossover ratio as needed.
3. Enable the TC1IE of the R7F/INTE register to enable interrupt and execute the EI command;
4. Enable TC1EN and enable TC1 timer counting;
5. The system will automatically save the ACC, STATUS and RSR data when executing the interrupt service program, and the data will be automatically restored after the RETI instruction is executed, and the TC1 interrupt flag should be cleared before exiting the interrupt;
TC1 Timing Calculation Description
The TC1 timing function executes an interrupt service program by writing a value to the TC1PRD register, which accumulates from the initial value of 0x01 until the timer meter value matches the value of the TC1PRD register.
TC1 timer calculation formula:
TC1
Timed time = 1/Fosc × (TC1
Frequency) × (TC1PRD − 1)
Example:
Fosc=8 MHz, TC1 divide-by-choice = 8-divide, TC1PRD value=255;
TC1 timing time = 1/8×8× (512 − 1)= 254us
TC1 Idle Mode Wake Up Instructions
The TC1 can wake up in idle mode, enable the R7E/SYSCON register Bit2-bit TC1WE, and select the TC1 clock source as the system clock. IDLE = 1 PLUS THE SLEEP COMMAND SYSTEM GOES INTO IDLE MODE, AND THE TC1 TIMER WORKS NORMALLY. When the TC1 timer overflows, the system is woken up. If TC1IE and EI are enabled, it will wake up and enter an interrupt, and if DI is executed, it will wake up and execute the next command.
PWM pulse width modulation
JZ8PE255E provides 3 8-bitPWM signals with a total period to generate a pulse-width modulated signal, and the PWM output waveform is determined by the period and duty cycle, and the transmission rate is the reciprocal of the period. The chip provides a dead-zone complementary output, which is XOR via PWM2 and PWM3 as IPWM1 and with PWM1 as a dead-zone complementary signal.
PWM has a periodic overflow interrupt that can be jumped to interrupt when enabled.
In IDLE (idle mode), PWM can wake up the system by selecting TC1CKS=1 in the CPU mode control register and enabling TC1WE.
PWM internal structure and timing
The following internal structure diagram is for reference only and does not represent the actual circuit.
PWM operating structure circuit
Description of the 3-way co-cycle PWM timing
PWM period vs. duty cycle
PWM vs. IPWM timing explained
PWM provides a clock counter (TC1) with 8-bit programmable predivider as a baud rate clock generator for the PWM module. The TC1 counter function can be enabled by enabling the TC1EN in the PWM control register, via TC1PTEN and TC1PSR<2:0>Control bit for pre-crossover setting of the TC1 counter.
The PWM period is written to the PWM cycle register (TC1PRD), and when the value of the TC1 counter is equal to the value of the TC1PRD, the following event occurs in the next increment period
TC1 counter clears;
Corresponding to PWM output pin set high;
PWM Cycle Overflow Interrupt (if enabled);
The PWM duty cycle is latched by the PWM1DT/PWM2DT/PWM3DT to the DT/TC1 comparison register;
PWM period calculation formula:
PWM period = TC1PRD× (1
osc
) × (TC1 crossover).
Example:
TC1PRD=100, Fosc=8 MHz, TC1 divide selection=2 divide;
PWM period = 100×
× 2 = 25 us
The PWM duty cycle is written by writing a value to the PWM duty cycle registers (PWM1DT, PWM2DT, PWM3DT), and when the value of the TC1 counter overflows to zero, PWM1DT/PWM2DT/PWM3DT The value of is latched into the DT/TC1 comparison register. When DT/TC1 is compared to send
When the value of the memory is equal to the value of the TC1 counter, the PWM output pin is set low. The values of PWM1DT, PWM2DT, PWM3DT can be written at any time, but the values of the DT/TC1 comparison registers are only written on periodic overflow:
PWM duty cycle calculation metric formula:
PWM duty cycle = PWMxDT× (1
osc
) × (TC1 divider).
Example:
PWMxDT=50, Fosc=8 MHz, TC1 divide selection=2 divide;
PWM duty cycle = 50×
× 2 = 12.5 us
PWM Pulse Width Modulation Setup Instructions
Set the TC1CON register, select the corresponding timer as PWM mode, the crossover ratio of the timer, the clock source of the timer, etc.
Write the value of the RPAGE-R9 register, determining the period of that PWM channel;
Write the value of the PWMxDT register, determining the duty cycle of that PWM channel;
Enable the corresponding timer;
Enable or disable PWM-corresponding timer interrupt and issue "EI" or "DI" commands (if required);
EEPROM Modules
JZ8PE255E has an internal 64-Byte EEPROM. The contents of this type of memory cannot be directly mapped to registers, but are indirectly addressed through special function registers (SFRs). By giving the E2PADR register access address, the E2PCON register configures read and write operations, and reads or writes data in the corresponding read and write data registers. The chip implements the self-timing function of erasing and programming in hardware, without software query, saving code space. The EEPROM function module has a total of 4 SFR registers for reading, writing, and controlling:
E2PADR（EEPROM Address Register）
E2PCON（EEPROM Control Register）
E2PDAT（EEPROM Write data register）
E2PREAD（EEPROM Read Data Register）
Note:
The factory default data of EEPROM is 0xA5.
When the power supply voltage is less than 2.5v, there is a probability that data writing will fail, so make sure the chip works above 2.5v and the EEPROM can be used normally.
AfterenablingtheEEPROMreadstatus,wait2usbeforestartingtoread the EEPROM data.
EEPROM Application Description Read Data Operation
SettheE2PCONregistertosetth ereadingspeedasneed ed;
Set the address to be read to E2PADR;
Set the read enable flag E2PRDEN to 1;
ReadthevalueoftheE2PREADre gister;
Clear the read enable flag E2PRDEN;
Write data operation
Set the E2PCON register to set the wake-up enable as needed (with
E2PIE, it can jump to the interrupt after wake-up);
Set the address to be written to E2PADR;
Assign the value to be written to E2PDAT;
Set the write enable flag E2PWREN to 1;
Wait for writing to be completed, and the write enable flag is automatically cleared by hardware (automatically cleared if writing fails);
Page 43 of 53
oPTION configuration table
CODE OPTION |
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| 2 Clocks |
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4 Clocks |
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8 Clocks |
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16 Clocks |
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32 Clocks |
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| 8M |
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1M |
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910KHz |
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| LVR=1.2V |
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LVR=1.6V |
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LVR=1.8V |
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LVR=2.4V |
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LVR=2.7V |
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LVR=3.1V |
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LVR=3.4V |
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LVR=3.7V |
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RST |
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| PWRT=WDT=4.5ms |
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PWRT=WDT=18ms |
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PWRT=WDT=72ms |
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PWRT=WDT=288ms |
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PWRT=140us,WDT=4.5ms |
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PWRT=140us,WDT=18ms |
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PWRT=140us,WDT=72ms |
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PWRT=140us,WDT=288ms |
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RTC |
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POWER | HIGH |
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LOW |
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Instruction set
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ADD A,R | A+R→A | Z,C,DC |
ADD R,A | A+R→R | Z,C,DC |
AND A,R | A&R→A | Z |
AND R,A | A&R→R | Z |
CLRA | 0→A | Z |
CLR R | 0→R | Z |
INVA R | /R→A | Z |
INV R | /R→R | Z |
DA |
| C |
DECA R | R-1→A | Z |
DEC R | R-1→R | Z |
DJA R | R-1→A, skip if zero | - |
DJ R | R-1→R, skip if zero | - |
INCA R | R+1→A | Z |
INC R | R+1→R | Z |
IJA R | R+1→A, skip if zero | - |
IJ R | R+1→R, skip if zero | - |
MOV R,A | A→R | - |
MOV A,R | R→A | Z |
MOV R,R | R→R | Z |
OR A,R | A∨VR→A | Z |
OR R,A | A∨VR→R | Z |
SUB A,R | R-A→A | Z,C,DC |
SUB R,A |
| Z,C,DC |
XOR A,R | A⊕R→A | Z |
XOR R,A | A⊕R→R | Z |
IR R | IOCR→A | - |
IW R | A→IOCR | - |
CTR | CONT→A | - |
CTW | A→CONT | - |
BTC R,b | 0→R(b) | - |
BTS R,b | 1→R(b) | - |
JBTC R,b | if R(b)=0, skip | - |
JBTS R,b | if R(b)=1, skip | - |
LCR R | R(n)→R(n+1),R(7)→C, C→R(0) | C |
LCA R | R(n)→A(n+1),R(7)→C, C→A(0) | C |
RCR R | R(n)→R(n-1),R(0)→C, C→R(7) | C |
RCA R | R(n)→A(n-1),R(0)→C, C→A(7) | C |
SWAP R | R(0-3) ↔ R(4-7) | - |
SWAPA R | R(0-3)→A(4-7),R(4-7)→A(0-3) | - |
ADD A,k | A+k→A | Z,C,DC |
AND A,k | A&k→A | Z |
MOV A,k | k→A | - |
OR A,k | A∨k→A | Z |
SUB A,k | k-A→A | Z,C,DC |
XOR A,k | A⊕k→A | Z |
CALL k | PC+1→[SP], (Page,k)→PC | - |
DI |
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EI |
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JMP k | K (Page,k)→PC | - |
NOP |
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RET |
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RETI |
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RETL k |
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SLEEP |
| T,P |
CWDT | 0→WDT | T,P |
Electro-pneumatic characteristics
Extremely limited parameters
Operating temperature........................................................... -40°C~85°C
Storage temperature.......................................................... -65°C~150°C
Input Voltage.................................................... Vss-0.3V～Vdd+0.5V
Output Voltage.................................................... Vss-0.3V～Vdd+0.5V
Operating Voltage............................................................. 1.8V-5.5V
Direct-flow electro-pneumatic characteristics
(V = 5V, working temperature = 25 °C, unless otherwise stated.) )
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IRCDD1 |
| OPTION 选择 8MHz | - | 8 | - | MHz |
IRC2 |
| OPTION 选择 1MHz | - | 1 | - | MHz |
IRC3 |
| OPTION 选择 910KHz | - | 910 | - | KHz |
Ioh1 |
| Ioh=4.4V | 5 | 5.5 | 6 |
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Ioh2 |
| Ioh=4.4V | 6 | 6.5 | 7 |
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Ioh3 |
| Ioh=4.4V | 12 | 14 | 16 |
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Iol1 |
| Iol=0.6V | 10 | 11 | 12 |
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Iol2 |
| Iol=0.6V | 19 | 21 | 23 |
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Iol3 |
| Iol=0.6V | 15 | 17 | 19 |
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Iol4 |
| Iol=0.6V | 24 | 26 | 28 |
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VIL1 |
| - | - | 1.3 | V | |
VIH1 |
| 2.6 | - | - | V | |
Rph1 |
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| - | 50 | - | KΩ |
Rph2 |
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| - | 100 | - | KΩ |
Rph3 |
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| - | 40 | - | KΩ |
Rph4 |
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| - | 75 | - | KΩ |
Rpd1 |
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| - | 90 | - | KΩ |
Rpd2 |
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| - | 166 | - | KΩ |
Isb1 |
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| - | - | 1 | µA |
Isb2 |
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| - | - | 10 | µA |
Iop2 |
| IRC=8MHz 2clock | - | 1.2 | 1.5 |
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Iop2 |
| IRC=910KHz 2clock | - | 0.2 | 0.3 |
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LVR |
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| Vlvr-0.2 | Vlvr | Vlvr+0.2 | V |
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Characteristic curved line diagram
The curve diagram listed in this chapter is for design reference only, and some of the data given therein may exceed the specified operating range of the chip, in order to ensure the normal operation of the chip, please strictly refer to the description of electrical characteristics
Internal low-speed RC oscillator-voltage characteristic curve
The operating temperature is in
25°C
Condition: (Units KHz)
Internal low-speed RC oscillator-temperature frequency characteristic curve
The operating voltage is in 5V
Condition: (Units KHz)
Internal 910KHzRC oscillator-voltage characteristic curve
Operating temperature at 25°C: (in KHz).
Internal 910KHzRC oscillator-temperature-frequency characteristic curve
Operating voltage at 5V: (in KHz).
Internal 8MHzRC oscillator-voltage characteristic curve
Operating temperature at 25°C: (in Mhz).
Internal 8MHzRC oscillator-temperature frequency characteristic curve
Operating voltage at 5V: (in Mhz).
Package size
8PIN package size
DIP8
6PIN package size
Symbol | mm | Inch | ||||
MIN | NOM | MAX | MIN | NOR | MAX | |
A | — | — | 1.35 | — | — | 0.053 |
A1 | 0.04 | — | 0.15 | 0.002 | — | 0.006 |
A2 | 1.00 | 1.10 | 1.20 | 0.039 | 0.043 | 0.047 |
A3 | 0.55 | 0.65 | 0.75 | 0.022 | 0.026 | 0.030 |
b | 0.30 | — | 0.50 | 0.013 | — | 0.017 |
b1 | 0.30 | 0.40 | 0.45 | 0.013 | 0.016 | 0.018 |
c | 0.08 | — | 0.22 | 0.006 | — | 0.008 |
c1 | 0.08 | 0.13 | 0.20 | 0.003 | 0.005 | 0.08 |
D | 2.72 | 2.92 | 3.12 | 0.107 | 0.115 | 0.123 |
E | 2.60 | 2.80 | 3.00 | 0.102 | 0.110 | 0.118 |
E1 | 1.40 | 1.60 | 1.80 | 0.055 | 0.063 | 0.071 |
e | 0.95BSC | 0.037BSC | ||||
L | 0.30 | — | 0.60 | 0.012 | — | 0.024 |
θ | 0 | — |
| 0 | — |
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