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智遨通（北京）信息技术有限公司刘博
Vivante.GC9x00.Series.Design.Specification.PPU.Work.Distributor-v0.81-E1.RestrictedDistribution-20250604
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最近修改: 7月4日 20:21
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  1. VERISILICONLEVEL E1: INTERNAL USE ONLY - RESTRICTED DISTRIBUTIONVivante GC9x00 SeriesDesign Specification:PPU Work DistributorVIVANTE INTERNAL USE ONLY DOCUMENTAuthorized Distribution Limited and RestrictedNote: This document is an ongoing work in progress.Internal review is ongoing and therefore content is subject to change.Document Revision 0.814 June 2025This document is compatible with the following IP variants:Vivante GC9x00, GC9x00-TC, GC9x00L, and GC9x00L-TC V9.0.x
  2. Vivante GC9x00 Series Design Specification: PPU Work DistributorPage 2 of 125Rev. 0.81 / June 2025VERISILICON LEVEL E1: INTERNAL USE ONLY - RESTRICTED DISTRIBUTIONLegal NoticesCOPYRIGHT INFORMATIONThis document contains proprietary information of Vivante Corporation and VeriSilicon Holdings Co., Ltd. They reserve the right to make changes to any products herein at any time without notice and do not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by Vivante and/or VeriSilicon; nor does the purchase or use of a product from Vivante or VeriSilicon convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of Vivante, VeriSilicon or third parties.DISCLOSURE/RE-DISTRIBUTION LIMITATIONSThe information contained herein is intended for internal VeriSilicon use only. The content is not to be used by or disclosed to third parties.(VeriSilicon Distribution LEVEL E1: INTERNAL USE ONLY – RESTRICTED DISTRIBUTION).Authorized distribution of this document is restricted.Vivante should be notified of any such re-distributions.TRADEMARK ACKNOWLEDGMENTVeriSilicon® and the VeriSilicon logo design are the trademarks or the registered trademarks of VeriSilicon Holdings Co., Ltd. Vivante® is a registered trademark of Vivante Corporation. All other brand and product names may be trademarks of their respective companies.For our current distributors, sales offices, design resource centers, and product information, visit our web page located at http://www.verisilicon.com.Vivante and VeriSilicon Proprietary. Copyright © 2025 by Vivante Corporation and VeriSilicon Holdings Co., Ltd. All rights reserved.
  3. Vivante GC9x00 Series Design Specification: PPU Work DistributorPage 3 of 125Rev. 0.81 / June 2025VERISILICON LEVEL E1: INTERNAL USE ONLY - RESTRICTED DISTRIBUTIONPrefaceThis internal document is a reference for the Vivante PPU work distributor unit.Audience: This document is intended for internal use only.Conventions which may be used in this documentAttrAC Attribute Allocation ControllerCS Computing ShaderFE Graphics Pipeline Front EndGPIPE VS, Tessellation Geometry PipelineGS Geometry ShaderOCF Output Control FIFOPA Primitive AssemblySW SoftwareTCS Tessellation Control Shader TFB Transform Feedback TES Tessellation Evaluation Shader TPG Tessellation Primitive GeneratorVS Vertex Shader CWD Cluster Work DistributorRA RasterThe word assert means to drive a signal true or active. Signals that are active LOW end in an “n.”Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF.Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111Code snippets are given in Consolas typeset.
  4. Vivante GC9x00 Series Design Specification: PPU Work DistributorPage 4 of 125Rev. 0.81 / June 2025VERISILICON LEVEL E1: INTERNAL USE ONLY - RESTRICTED DISTRIBUTIONTable of ContentsLEGAL NOTICES ...................................................................................................................................................... 2PREFACE ................................................................................................................................................................ 3TABLE OF CONTENTS.............................................................................................................................................. 4LIST OF FIGURES..................................................................................................................................................... 8LIST OF TABLES .................................................................................................................................................... 101 PWD OVERVIEW..................................................................................................................................... 111.1 Introduction ...........................................................................................................................................111.2 PWD Top Diagram..................................................................................................................................121.3 PWD Feature List....................................................................................................................................121.4 Target Performance ...............................................................................................................................152 STATE LOAD FLOW................................................................................................................................. 162.1 Overview ................................................................................................................................................162.2 Graphic State-Load Flow ........................................................................................................................172.3 Compute State-Load Flow......................................................................................................................202.4 PWD State Load Flow .............................................................................................................................223 PWD VS BATCH DISTRIBUTION (PVBD)................................................................................................... 233.1 Function .................................................................................................................................................233.1.1 State-Load Path........................................................................................................................243.1.2 VS Batch Path...........................................................................................................................253.1.3 DPPU ID Path............................................................................................................................253.1.4 Token .......................................................................................................................................253.2 Round Robin Arbitrator..........................................................................................................................253.3 Output Control .......................................................................................................................................273.4 Interface .................................................................................................................................................284 PWD TPG BATCH DISTRIBUTION (PTBD)................................................................................................. 314.1 Function .................................................................................................................................................314.1.1 State-Load Path........................................................................................................................324.1.2 TPG Batch Path ........................................................................................................................324.1.3 DPPU ID Path............................................................................................................................324.1.4 Token .......................................................................................................................................324.2 Round Robin Arbitrator..........................................................................................................................334.3 Data Split................................................................................................................................................344.4 Output Control .......................................................................................................................................354.5 Interface .................................................................................................................................................365 PWD COMPUTE BATCH DISTRIBUTION (PCBD)....................................................................................... 395.1 Function .................................................................................................................................................395.1.1 State-Load Path........................................................................................................................395.1.2 CL WG Batch Path ....................................................................................................................405.2 Target Performance ...............................................................................................................................405.3 Sub-Module Description ........................................................................................................................415.3.1 Output Control.........................................................................................................................415.4 Token......................................................................................................................................................425.5 FIFOs.......................................................................................................................................................425.6 Interface .................................................................................................................................................426 PWD PS BATCH DISTRIBUTION (PPBD) ................................................................................................... 44
  5. Vivante GC9x00 Series Design Specification: PPU Work DistributorPage 5 of 125Rev. 0.81 / June 2025VERISILICON LEVEL E1: INTERNAL USE ONLY - RESTRICTED DISTRIBUTION6.1 Overview ................................................................................................................................................446.1.1 State-Load Path........................................................................................................................456.1.2 PS Batch Path ...........................................................................................................................466.1.3 FIFO Read Control ....................................................................................................................466.2 Token......................................................................................................................................................476.3 FIFOs.......................................................................................................................................................486.4 Interface .................................................................................................................................................487 PWD LOAD BALANCE MANAGER (PLBM)................................................................................................ 507.1 LBM Overview ........................................................................................................................................507.2 State-Loads.............................................................................................................................................507.2.1 State-Load Update ...................................................................................................................507.2.2 State-Loads for LBMs...............................................................................................................517.3 Temp Registers in Use Update ...............................................................................................................517.3.1 Temp Table ..............................................................................................................................517.3.2 Allocation .................................................................................................................................537.3.3 Deallocation and Correction ....................................................................................................567.4 Batch Distribution ..................................................................................................................................567.4.1 General Comparator ................................................................................................................567.4.2 CWD Comparator.....................................................................................................................577.4.3 PPBD Comparator ....................................................................................................................597.5 PLBM ......................................................................................................................................................597.5.1 Calculation ...............................................................................................................................607.5.2 Accumulator & Phase Mag.......................................................................................................607.6 LBM Supplementary...............................................................................................................................607.6.1 Comparator Table Modify........................................................................................................607.6.2 Update Strategy Modify...........................................................................................................617.6.3 Arbitration................................................................................................................................627.7 PLBM Interface.......................................................................................................................................628 TCS BATCH RBE ALLOCATION REORDER (TRARO) ................................................................................... 648.1 Function .................................................................................................................................................648.2 Reorder ..................................................................................................................................................648.3 FIFOs.......................................................................................................................................................658.4 Interface .................................................................................................................................................659 IN-CLUSTER TPG BATCH REORDER (ICTRO)............................................................................................. 679.1 Function .................................................................................................................................................679.2 Reorder ..................................................................................................................................................689.3 FIFO Control ...........................................................................................................................................689.3.1 FIFO Push .................................................................................................................................689.3.2 FIFO Pop...................................................................................................................................699.3.3 FIFO Depth ...............................................................................................................................709.4 Interface .................................................................................................................................................7010 PA INPUT REORDER (PAIRO) .................................................................................................................. 7210.1 Function .................................................................................................................................................7210.2 Reorder ..................................................................................................................................................7310.3 FIFOs Control..........................................................................................................................................7410.3.1 FIFO Push Control ....................................................................................................................7410.3.2 FIFO Pop Control......................................................................................................................7510.3.3 FIFO Depth ...............................................................................................................................7610.4 Interface .................................................................................................................................................76
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Vivante GC9x00 Series Design Specification: PPU Work DistributorPage 6 of 125Rev. 0.81 / June 2025VERISILICON LEVEL E1: INTERNAL USE ONLY - RESTRICTED DISTRIBUTION11 IN-CLUSTER PRIM BATCH REORDER (ICPRO)........................................................................................... 7811.1 Function .................................................................................................................................................7811.2 Reorder ..................................................................................................................................................7811.3 FIFO Control ...........................................................................................................................................7911.3.1 FIFO Push Control ....................................................................................................................7911.3.2 FIFO Pop Control......................................................................................................................8011.3.3 FIFO Depth ...............................................................................................................................8111.4 Interface .................................................................................................................................................8212 PS BATCH DATA REORDER (PSDRO)........................................................................................................ 8412.1 Overview ................................................................................................................................................8412.1.1 DPPU ID Arbitration .................................................................................................................8512.1.2 Reorder ....................................................................................................................................8512.1.3 State Processing.......................................................................................................................8612.2 FIFOs.......................................................................................................................................................8612.2.1 PS Waiting FIFO........................................................................................................................8612.2.2 State InFIFO..............................................................................................................................8712.2.3 DPPU InFIFO.............................................................................................................................8712.2.4 FIFOs and RAMs.......................................................................................................................8812.3 Interface .................................................................................................................................................8813 TFB REORDER (TFBRO) ........................................................................................................................... 9013.1 Function .................................................................................................................................................9013.1.1 TFB ID Gen................................................................................................................................9113.1.2 Reorder ....................................................................................................................................9113.1.3 TFB Request .............................................................................................................................9313.2 Token......................................................................................................................................................9313.3 FIFOs.......................................................................................................................................................9313.3.1 Waiting FIFO.............................................................................................................................9313.3.2 DPPU InFIFO.............................................................................................................................9413.3.3 FIFO Summary..........................................................................................................................9513.4 Interface .................................................................................................................................................9514 TPG BATCH RBE DEALLOCATION MANAGER (TRDM).............................................................................. 9714.1 Function .................................................................................................................................................9714.1.1 RBE Table .................................................................................................................................9814.1.2 Table In Mag ............................................................................................................................9914.1.3 RBE Release Mag....................................................................................................................10014.1.4 Merge Out..............................................................................................................................10314.2 FIFOs and RAMs ...................................................................................................................................10414.3 Interface ...............................................................................................................................................10415 PRIMITIVE RBE DEALLOCATION MANAGER (PRDM) ............................................................................. 10615.1 Function ...............................................................................................................................................10615.1.1 RBE Table ...............................................................................................................................10715.1.2 Table In Mag ..........................................................................................................................10815.1.3 RBE Deallocation Mag............................................................................................................10915.2 FIFOs and RAMs ...................................................................................................................................11115.3 Interface ...............................................................................................................................................11116 PWD COMPUTE SYNC REORDER (PCSRO) ............................................................................................. 11316.1 Introduction .........................................................................................................................................11316.2 Feature List...........................................................................................................................................11316.3 Interface ...............................................................................................................................................114
  7. Vivante GC9x00 Series Design Specification: PPU Work DistributorPage 7 of 125Rev. 0.81 / June 2025VERISILICON LEVEL E1: INTERNAL USE ONLY - RESTRICTED DISTRIBUTION16.3.1 Top Level Interface ................................................................................................................11416.4 Collector...............................................................................................................................................11516.4.1 Semaphore Collector .............................................................................................................11516.4.2 Collector of Event, Fence, and qbarrier.................................................................................11516.4.3 Collector of draw_id and queue_id .......................................................................................11617 PWD GRAPHIC SYNC REORDER (PGSRO)............................................................................................... 11717.1 Introduction .........................................................................................................................................11717.2 Feature List...........................................................................................................................................11717.3 Interface ...............................................................................................................................................11817.3.1 Top Level Interface ................................................................................................................11817.4 Collector...............................................................................................................................................12017.4.1 Semaphore Collector .............................................................................................................12017.4.2 Other Collectors.....................................................................................................................120DOCUMENT REVISION HISTORY......................................................................................................................... 122
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