AC97

AC97 is a commonly found interface on many PC cards, it's not that popular in embedded devices though. It's a five wire interface with:
AC97 是在許多 PC 卡上常見的介面，但在嵌入式裝置中並不那麼普及。它是一個五線介面，包含：

• A reset line  重置線
• DATA_OUT for playback  播放用的 DATA_OUT
• SDATA_IN for capture  錄音用的 SDATA_IN
• BCLK as bit clock, which is always driven by the CODEC
  BCLK 作為位元時鐘，始終由 CODEC 驅動

See the specification [4] for further reading.
詳見規格書 [4] 以獲取更多資訊。

I2S

I2S is a common 5 wire DAI often used in embedded systems. The TX (SDOUT) and Rx (SDIN) lines are used for audio transmission while the bit and frame clock are used for synchronization.
I2S 是一種常見的五線數位音訊介面（DAI），常用於嵌入式系統。TX（SDOUT）和 RX（SDIN）線用於音訊傳輸，而位元時鐘和框架時鐘則用於同步。

The signals are:  訊號包括：

• Master clock or system clock, often referred to as MCLK, is the clock which the other clocks is derived from. This also clock the CODEC.
  主時鐘或系統時鐘，通常稱為 MCLK，是其他時鐘的來源時鐘。這個時鐘也用來驅動 CODEC。
• Bit clock, often referred to as BCK or BCLK, varies depending on the sample rate.
  位元時鐘，通常稱為 BCK 或 BCLK，會根據取樣率而變化。
• Frame clock, often referred to ass LRCLK (Left-Right Clock), FCLK (Frame clock) or WCLK (Word clock).
  框架時鐘，通常稱為 LRCLK（左右聲道時鐘）、FCLK（框架時鐘）或 WCLK（字時鐘）。
• Audio out, SDOUT  音訊輸出，SDOUT
• Audio In, SDIN  音訊輸入，SDIN

The relationship between BCLK and LRCLK is
BCLK 與 LRCLK 之間的關係是

bclk = (sample rate) * Nchannels * (bit depth)

Some CODECs are able to use BCLK as their only clock, which leaving MCLK as optional. The CODEC we will use does supports this and is something we have to use due to HW constraints in number of available signals that should fit in a connector.
有些 CODEC 能夠只使用 BCLK 作為唯一時鐘，將 MCLK 設為可選。我們將使用的 CODEC 支援此功能，且由於硬體限制（可用訊號數量需符合連接器規格），我們必須採用此方式。

This is an illustration of the timing on the I2S bus with 64 BCLKs per LRCLK. Borrowed from the datasheet [5]:
以下是 I2S 匯流排上每個 LRCLK 對應 64 個 BCLK 的時序示意圖。資料來源借用自規格書 [5]：

I2S could be used with TDM format timing to support more audio channels on the same I2S bus. The timing will then look like this [5] :
I2S 可以搭配 TDM 格式時序使用，以支援在同一條 I2S 線路上更多的音訊通道。時序將會如下所示 [5] ：

PCM

PCM is a 4 wire interface that is quite similar to I2S. Same same but different.
PCM 是一種四線介面，與 I2S 相當相似。相同中帶有差異。

Clocks  時鐘

We have several clocks such as bit clock, frame clock and master clock. It's not written in stone which endpoint of the DAI that should generate these clocks, it's up to us to decide.
我們有多種時鐘，例如位元時鐘、框架時鐘和主時鐘。並沒有規定 DAI 的哪一端點必須產生這些時鐘，這由我們自行決定。

Either the SoC or CODEC generates some or all of the clocks, called clock master (e.g. bit clock master or frame clock master).
無論是 SoC 或 CODEC 都可以產生部分或全部時鐘，稱為時鐘主控（例如位元時鐘主控或框架時鐘主控）。

It's often easiest to let the CODEC generate all clocks, but some SoCs has specialized audio PLLs for this. In our case, the SoC will be clock master.
通常讓 CODEC 產生所有時鐘是最簡單的，但有些 SoC 具有專門的音訊 PLL。以我們的情況來說，SoC 將擔任時鐘主控。

The SoC  SoC

The board we are going to use is an evaluation board for a i.MX8MM module [2]. The CPU module supports two I2S busses and we are going to use one of them.
我們將使用的開發板是針對 i.MX8MM 模組的評估板 [2]。該 CPU 模組支援兩個 I2S 匯流排，我們將使用其中一個。

The CODEC  編解碼器

The CODEC we will use is is the TAS5720L [3] from Texas Instruments which has been supported in mainline since v4.6.
我們將使用的 CODEC 是來自德州儀器的 TAS5720L [3]，自 v4.6 版本起已在主線內核中獲得支援。

The TAS5720L device Serial Audio Interface (SAIF) supports a variety of audio formats including I2S, left-justified and Right justified. It also supports the time division multiplexed (TDM) format that is capable of transporting up to 8 channels of audio data on a single bus.
TAS5720L 裝置的串列音訊介面（SAIF）支援多種音訊格式，包括 I2S、左對齊及右對齊格式。它也支援時分多工（TDM）格式，能夠在單一匯流排上傳輸最多 8 聲道的音訊資料。

It uses I2C as configuration interface.
它使用 I2C 作為配置介面。

We will use I2S with TDM as DAI and I2C as configuration interface.
我們將使用 I2S 搭配 TDM 作為 DAI，並使用 I2C 作為配置介面。

SAI node  SAI 節點

The Synchronous Audio Interface (SAI) module is the HW part of the i.MX8 SoC that are used to generate the digital audio.
同步音訊介面（SAI）模組是 i.MX8 SoC 中用於產生數位音訊的硬體部分。

We are going to use the SAI5 interface as it's routed from the sm2s-imx8mm module. The node is properly configured in an interface (.dtsi)-file, so we only have to enable it:
我們將使用 SAI5 介面，因為它是從 sm2s-imx8mm 模組路由出來的。該節點已在介面（.dtsi）檔案中正確配置，因此我們只需啟用它：

&sai5 {
    status = "okay";
};

CODEC node  CODEC 節點

The TAS5720L is connected to the I2C3 bus and respond to the slave address 0x6c. Besides the compatible and reg properties, the node also requires phandle for a 3V3 supply that supplies the digital circuitry and a phandle for the Class-D amp and analog part.
TAS5720L 連接到 I2C3 匯流排並回應從屬位址 0x6c。除了 compatible 和 reg 屬性外，該節點還需要一個用於供應數位電路的 3V3 電源的 phandle，以及一個用於 Class-D 擴大機和類比部分的 phandle。

The hardware does not have such controllable supplies so we have to create fixed regulators for that:
硬體沒有這種可控電源，因此我們必須為此建立固定的穩壓器：

/ {
    reg_audio_p: regulator-audio {
        compatible = "regulator-fixed";
        regulator-name = "audio power";
        pinctrl-names = "default";
        regulator-min-microvolt = <12000000>;
        regulator-max-microvolt = <12000000>;
    };

    reg_audio_d: regulator-audio {
        compatible = "regulator-fixed";
        regulator-name = "audio digital";
        pinctrl-names = "default";
        regulator-min-microvolt = <3300000>;
        regulator-max-microvolt = <3300000>;
    };
};

And the device node for the CODEC itself:
以及 CODEC 本身的裝置節點：

&i2c3 {

    tas5720: tas5720@6c {
            #sound-dai-cells = <0>;
            reg = <0x6c>;
            compatible = "ti,tas5720";

            dvdd-supply = <&reg_audio_d>;
            pvdd-supply = <&reg_audio_p>;
    };
};

Sound node  聲音節點

Now it's time to setup the sound node!
現在是時候設定聲音節點了！

First we have to specify which audio format we intend to use by setting simple-audio-card,format to i2s.
首先，我們必須透過設定 simple-audio-card,format 為 i2s 來指定我們打算使用的音訊格式。

We also have to setup the two DAIs (CPU & CODEC) that we are going to use.
我們也必須設定將要使用的兩個 DAI（CPU 與 CODEC）。

This is done by creating sub nodes and refer to the SAI module node and CODEC node as sound-dai respectively.
這是透過建立子節點並分別參考 SAI 模組節點與 CODEC 節點作為 sound-dai 來完成的。

These sub nodes are referred to when assign frame-master and bitclock-master in the sound node. As we want the SoC to generate both frame- and bit-clock, set cpudai as clock master for both.
這些子節點會在聲音節點中指定 frame-master 和 bitclock-master 時被引用。由於我們希望 SoC 產生 frame-clock 和 bit-clock，故將 cpudai 設為兩者的時鐘主控。

/ {
    sound-tas5720 {
        compatible = "simple-audio-card";
        simple-audio-card,name = "tas5720-audio";
        simple-audio-card,format = "i2s";
        simple-audio-card,frame-master = <&cpudai>;
        simple-audio-card,bitclock-master = <&cpudai>;

        cpudai: simple-audio-card,cpu {
            sound-dai = <&sai5>;
            clocks = <&clk IMX8MM_CLK_SAI5_ROOT>;

        };

        simple-audio-card,codec {
            sound-dai = <&tas5720>;
            clocks = <&clk IMX8MM_CLK_SAI5_ROOT>;
        };
    };
};

Debug clock signals  除錯時鐘訊號

Lets look what our clock tree looks like:
讓我們來看看我們的時鐘樹長什麼樣子：

root@imx8board:~# cat /sys/kernel/debug/clk/clk_summary
    ...
    audio_pll2_ref_sel                0        0        0    24000000          0     0  50000
       audio_pll2                     0        0        0   361267200          0     0  50000
          audio_pll2_bypass           0        0        0   361267200          0     0  50000
             audio_pll2_out           0        0        0   361267200          0     0  50000
    audio_pll1_ref_sel                0        0        0    24000000          0     0  50000
       audio_pll1                     0        0        0   393216000          0     0  50000
          audio_pll1_bypass           0        0        0   393216000          0     0  50000
             audio_pll1_out           0        0        0   393216000          0     0  50000
                sai5                  0        0        0    24576000          0     0  50000
                   sai5_root_clk       0        0        0    24576000          0     0  50000
    ...

The sai5 clock is running at 24576000Hz, and indeed, it's hard to find a working clock divider to get 1411200Hz.
sai5 時鐘運行頻率為 24576000Hz，確實很難找到一個可用的時鐘分頻器來得到 1411200Hz。

audio_pll2 @ 361267200 looks better. 361267200/1411200=256, allmost perfect!
audio_pll2 @ 361267200 看起來比較好。361267200/1411200=256，幾乎完美！

Then we need to reparent the sai5 module, this is done in the device tree as well:
接著我們需要重新指定 sai5 模組的父節點，這也在裝置樹中完成：

&sai5 {
    status = "okay";
    assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
    assigned-clock-rates = <11289600>;
};

Here is our new clock tree:
這是我們新的時鐘樹：

root@imx8board:~# cat /sys/kernel/debug/clk/clk_summary
    ...
    audio_pll2_ref_sel                0        0        0    24000000          0     0  50000
       audio_pll2                     0        0        0   361267200          0     0  50000
          audio_pll2_bypass           0        0        0   361267200          0     0  50000
             audio_pll2_out           0        0        0   361267200          0     0  50000
                sai5                  0        0        0    11289600          0     0  50000
                   sai5_root_clk       0        0        0    11289600          0     0  50000
    ...

We can see that the frequency is right and also that we now derive our clock from audio_pll2_out instead of audio_pll1.
我們可以看到頻率是正確的，並且我們現在是從 audio_pll2_out 而非 audio_pll1 取得時鐘。

The speaker-test software is also happier:
speaker-test 軟體也更順利了：

root@imx8board:~# speaker-test

speaker-test 1.2.5.1

Playback device is default
Stream parameters are 44000Hz, S16_LE, 1 channels
Using 16 octaves of pink noise
Rate set to 44000Hz (requested 44000Hz)
Buffer size range from 3840 to 5760
Period size range from 1920 to 1920
Using max buffer size 5760
Periods = 4
was set period_size = 1920
was set buffer_size = 5760
 0 - Front Left

Great!  太棒了！

Use BCLK as MCLK
使用 BCLK 作為 MCLK

Due to my hardware constraints, I need to use the bit clock as master clock. If we look in the datasheet [5] :
由於我的硬體限制，我需要使用位元時鐘作為主時鐘。如果我們查看資料表 [5]：

If the BCLK to LRCLK ratio is 64, we could tie MCLK directly to our BCLK!
如果 BCLK 與 LRCLK 的比率是 64，我們可以直接將 MCLK 綁定到 BCLK！

We already know our BCLK, it's 1411200Hz, and the frame clock (LRCLK) is the same as the sample rate (44kHz). We could verify that with the oscilloscope.
我們已經知道我們的 BCLK 是 1411200Hz，框架時鐘（LRCLK）與取樣率（44kHz）相同。我們可以用示波器來驗證這一點。

Bitclock:

Frameclock:  框架時鐘：

That is not a ratio of 64.
那不是 64 的比例。

There is not much to do about the frame clock, it will stick to the sample rate. If we make use of TDM though, we can make the bit clock running faster with the same frame clock!
對於框架時鐘沒什麼好做的，它會固定在取樣率上。不過如果我們使用 TDM，就可以讓位元時鐘在相同框架時鐘下運行得更快！

Lets add 2 TDM slots @ 32bit width:
讓我們新增 2 個 32 位元寬度的 TDM 時隙：

/ {
    sound-tas5720 {
        compatible = "simple-audio-card";
        simple-audio-card,name = "tas5720-audio";
        simple-audio-card,format = "i2s";
        simple-audio-card,frame-master = <&cpudai>;
        simple-audio-card,bitclock-master = <&cpudai>;

        cpudai: simple-audio-card,cpu {
            sound-dai = <&sai5>;
            clocks = <&clk IMX8MM_CLK_SAI5_ROOT>;
            dai-tdm-slot-num = <2>;
            dai-tdm-slot-width = <32>;
        };

        simple-audio-card,codec {
            sound-dai = <&tas5720>;
            clocks = <&clk IMX8MM_CLK_SAI5_ROOT>;
        };
    };
};

Verify the bitclock:  驗證位時鐘：

Lets calculate: 2820000/44000 ~= 64! We have reached our goal!
讓我們計算一下：2820000/44000 ≈ 64！我們達成目標了！